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Starred by 35 users

Issue metadata

Status: WontFix
Owner:
Closed: Feb 2017
Cc:
HW: ----
NextAction: ----
OS: ----
Priority: 2
Type: Bug



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Implement SIMD.js

Project Member Reported by bradnelson@chromium.org, May 18 2015

Issue description

We should implement SIMD.js behind a flag.

This issue will track the overall implementation.

SPEC
John Mccutchan’s Strawman proposal:
https://github.com/johnmccutchan/ecmascript_simd

SUMMARY
SIMD.js exposes hardware SIMD instructions to Javascript applications in a platform-independent way. Add three SIMD vector types: float32x4, float64x2, and int32x4, and corresponding Typed Array views.

MOTIVATION
SIMD.js can speed up applications that process lots of data that is naturally organized as 2, 3, or 4 element vectors. SIMD is also useful when compiling native code to Javascript for static compilation by the Javascript engine.

COMPATIBILITY RISK
Mozilla has implemented this in Firefox:
https://hacks.mozilla.org/2014/10/introducing-simd-js/
https://blog.mozilla.org/javascript/2015/03/10/state-of-simd-js-performance-in-firefox/

Microsoft have announced plans to implement SIMD.js in Spartan.
Slides:  http://channel9.msdn.com/Events/Build/2015/2-763
Video: http://video.ch9.ms/sessions/build/2015/2-763-LG.mp4

SIMD.js discussion starts at minute 45:35 and demoed with Mandelbrot at time 49:00.

 
Showing comments 63 - 162 of 162 Older
Project Member

Comment 64 by bugdroid1@chromium.org, May 19 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/479de28c3aea08643a371097c480eb73e81c6930

commit 479de28c3aea08643a371097c480eb73e81c6930
Author: machenbach <machenbach@chromium.org>
Date: Thu May 19 08:58:01 2016

Revert of Adding ia32 simd assembler changes. (patchset #2 id:20001 of https://codereview.chromium.org/1991713002/ )

Reason for revert:
Crashes on win32 debug:
https://build.chromium.org/p/client.v8/builders/V8%20Win32%20-%20debug/builds/2305/steps/Check/logs/stdio

Also, would be nice if the test output could be a bit shorter and only print what's necessary to trace a failure. Or split things into more smaller tests. Like that, these logs must be processed, json-encoded/decoded and sent around through the infrastructure.

Some chars in the output make the json encoder unhappy, therefore the infrastructure can't nicely display the failures.

Original issue's description:
> Adding ia32 simd assembler support.
>
> Based on assembler changes from this patch:
> https://codereview.chromium.org/90643003/
>
> BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124
> R=titzer@chromium.org
> LOG=N
>
> Committed: https://crrev.com/fbf58a5af1d07a7fbb3763aa15f8ba26e2ce7d11
> Cr-Commit-Position: refs/heads/master@{#36349}

TBR=bbudge@chromium.org,titzer@chromium.org,gdeepti@chromium.org,aseemgarg@chromium.org,bradnelson@chromium.org
# Skipping CQ checks because original CL landed less than 1 days ago.
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true
BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124

Review-Url: https://codereview.chromium.org/1992163002
Cr-Commit-Position: refs/heads/master@{#36353}

[modify] https://crrev.com/479de28c3aea08643a371097c480eb73e81c6930/src/ia32/assembler-ia32.cc
[modify] https://crrev.com/479de28c3aea08643a371097c480eb73e81c6930/src/ia32/assembler-ia32.h
[modify] https://crrev.com/479de28c3aea08643a371097c480eb73e81c6930/src/ia32/disasm-ia32.cc
[modify] https://crrev.com/479de28c3aea08643a371097c480eb73e81c6930/test/cctest/test-disasm-ia32.cc

Project Member

Comment 67 by bugdroid1@chromium.org, May 27 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/f50d950052a51e2d4396d2d05392c971fb116538

commit f50d950052a51e2d4396d2d05392c971fb116538
Author: bbudge <bbudge@chromium.org>
Date: Fri May 27 18:39:45 2016

Turbofan: Rename UnallocatedOperand policies from '*DOUBLE*' to '*FP*'.

- Renames UnallocatedOperandenum values to reflect the fact that there are
multiple FP machine representations.
- Renames enum values for RegisterAllocatorVerifier enum.
- Template-izes DefineAsFixed and UseFixed methods to handle multiple FP
register types.

BUG=v8:4124

Review-Url: https://codereview.chromium.org/2017733002
Cr-Commit-Position: refs/heads/master@{#36558}

[modify] https://crrev.com/f50d950052a51e2d4396d2d05392c971fb116538/src/compiler/instruction-scheduler.h
[modify] https://crrev.com/f50d950052a51e2d4396d2d05392c971fb116538/src/compiler/instruction-selector-impl.h
[modify] https://crrev.com/f50d950052a51e2d4396d2d05392c971fb116538/src/compiler/instruction.cc
[modify] https://crrev.com/f50d950052a51e2d4396d2d05392c971fb116538/src/compiler/instruction.h
[modify] https://crrev.com/f50d950052a51e2d4396d2d05392c971fb116538/src/compiler/register-allocator-verifier.cc
[modify] https://crrev.com/f50d950052a51e2d4396d2d05392c971fb116538/src/compiler/register-allocator-verifier.h
[modify] https://crrev.com/f50d950052a51e2d4396d2d05392c971fb116538/src/compiler/register-allocator.cc

Project Member

Comment 71 by bugdroid1@chromium.org, Jun 3 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/b9ded4ce9cda2053d084e043e8a30a90ae3e801d

commit b9ded4ce9cda2053d084e043e8a30a90ae3e801d
Author: balazs.kilvady <balazs.kilvady@imgtec.com>
Date: Fri Jun 03 16:43:05 2016

MIPS: Fix 'Turbofan: Modify WASM linkage to store floats using only 4 bytes.'

Port 817b59c8ad7e9237d93a43a31045285418bbb6d5

Adds instructions for MIPS to push float (single) and double registers.

LOG=N
BUG=v8:4124
TEST=cctest/test-run-native-calls/Float32Select_stack_params_return_reg,
cctest/test-run-native-calls/MixedParams_0, cctest/test-run-native-calls/MixedParams_1,
cctest/test-run-native-calls/MixedParams_2, cctest/test-run-native-calls/MixedParams_3

Review-Url: https://codereview.chromium.org/2038813002
Cr-Commit-Position: refs/heads/master@{#36719}

[modify] https://crrev.com/b9ded4ce9cda2053d084e043e8a30a90ae3e801d/src/compiler/mips/code-generator-mips.cc

Project Member

Comment 73 by bugdroid1@chromium.org, Jun 13 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/24139633c88082de5db0b99b86e6c5178a7e4822

commit 24139633c88082de5db0b99b86e6c5178a7e4822
Author: bbudge <bbudge@chromium.org>
Date: Mon Jun 13 21:28:12 2016

[Turbofan] Eliminate unnecessary OperandComparer.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2067463003
Cr-Commit-Position: refs/heads/master@{#36944}

[modify] https://crrev.com/24139633c88082de5db0b99b86e6c5178a7e4822/src/compiler/move-optimizer.cc

Comment 74 by sehr@chromium.org, Jun 13 2016

Cc: -sehr@chromium.org
Project Member

Comment 75 by bugdroid1@chromium.org, Jun 14 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/fc59eb8a7a1eb45edd2d4ff7910e66fab3093030

commit fc59eb8a7a1eb45edd2d4ff7910e66fab3093030
Author: bbudge <bbudge@chromium.org>
Date: Tue Jun 14 12:26:59 2016

[tests] Don't test moves between different reps in test-gap-resolver.cc

Moves between operands with different representations shouldn't happen,
so don't test them. This makes it easier to modify canonicalization to
differentiate between floating point types, which is needed to support
floating point register aliasing for ARM and MIPS.

This change also expands tests to include explicit FP moves (both register and stack slot).

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2060273003
Cr-Commit-Position: refs/heads/master@{#36963}

[modify] https://crrev.com/fc59eb8a7a1eb45edd2d4ff7910e66fab3093030/test/cctest/compiler/test-gap-resolver.cc

Project Member

Comment 77 by bugdroid1@chromium.org, Jun 18 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/d99e1ab60557e86b62ccc6c91514e817c0df370d

commit d99e1ab60557e86b62ccc6c91514e817c0df370d
Author: bbudge <bbudge@chromium.org>
Date: Sat Jun 18 23:16:56 2016

[Turbofan] Clean up register allocator and verifier code.

- Improves RegisterName display in register allocator.
- Removes GetFixedRegisters method in preparation for having multiple fp
reg types.
- Clean up some verifier code.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2081443002
Cr-Commit-Position: refs/heads/master@{#37076}

[modify] https://crrev.com/d99e1ab60557e86b62ccc6c91514e817c0df370d/src/compiler/register-allocator-verifier.h
[modify] https://crrev.com/d99e1ab60557e86b62ccc6c91514e817c0df370d/src/compiler/register-allocator.cc
[modify] https://crrev.com/d99e1ab60557e86b62ccc6c91514e817c0df370d/src/compiler/register-allocator.h

Project Member

Comment 78 by bugdroid1@chromium.org, Jun 19 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/a17f3d248e247cda8e51344ce6f426e93ab97284

commit a17f3d248e247cda8e51344ce6f426e93ab97284
Author: machenbach <machenbach@chromium.org>
Date: Sun Jun 19 07:36:01 2016

Revert of [Turbofan] Clean up register allocator and verifier code. (patchset #1 id:1 of https://codereview.chromium.org/2081443002/ )

Reason for revert:
[Sheriff] Speculative revert. Looks like this lets a few ignition+turbofan tests time out under tsan:
https://build.chromium.org/p/client.v8/builders/V8%20Linux64%20TSAN/builds/10171

Original issue's description:
> [Turbofan] Clean up register allocator and verifier code.
>
> - Improves RegisterName display in register allocator.
> - Removes GetFixedRegisters method in preparation for having multiple fp
> reg types.
> - Clean up some verifier code.
>
> LOG=N
> BUG=v8:4124
>
> Committed: https://crrev.com/d99e1ab60557e86b62ccc6c91514e817c0df370d
> Cr-Commit-Position: refs/heads/master@{#37076}

TBR=mtrofin@chromium.org,bbudge@chromium.org
# Skipping CQ checks because original CL landed less than 1 days ago.
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2078243002
Cr-Commit-Position: refs/heads/master@{#37077}

[modify] https://crrev.com/a17f3d248e247cda8e51344ce6f426e93ab97284/src/compiler/register-allocator-verifier.h
[modify] https://crrev.com/a17f3d248e247cda8e51344ce6f426e93ab97284/src/compiler/register-allocator.cc
[modify] https://crrev.com/a17f3d248e247cda8e51344ce6f426e93ab97284/src/compiler/register-allocator.h

Project Member

Comment 79 by bugdroid1@chromium.org, Jun 24 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/5cda2db7d3ca954733a82cb203d46d2f6f73484c

commit 5cda2db7d3ca954733a82cb203d46d2f6f73484c
Author: balazs.kilvady <balazs.kilvady@imgtec.com>
Date: Fri Jun 24 08:23:52 2016

Fix '[tests] Don't test moves between different reps in test-gap-resolver.cc'

Port fc59eb8a7a1eb45edd2d4ff7910e66fab3093030

Original commit message:
Moves between operands with different representations shouldn't happen,
so don't test them. This makes it easier to modify canonicalization to
differentiate between floating point types, which is needed to support
floating point register aliasing for ARM and MIPS.

This change also expands tests to include explicit FP moves (both register and stack slot).

LOG=N
BUG=v8:4124
BUG=chromium:622619

Review-Url: https://codereview.chromium.org/2090993002
Cr-Commit-Position: refs/heads/master@{#37241}

[modify] https://crrev.com/5cda2db7d3ca954733a82cb203d46d2f6f73484c/src/arm/assembler-arm.h
[modify] https://crrev.com/5cda2db7d3ca954733a82cb203d46d2f6f73484c/src/arm64/assembler-arm64.h
[modify] https://crrev.com/5cda2db7d3ca954733a82cb203d46d2f6f73484c/src/assembler.cc
[modify] https://crrev.com/5cda2db7d3ca954733a82cb203d46d2f6f73484c/src/assembler.h
[modify] https://crrev.com/5cda2db7d3ca954733a82cb203d46d2f6f73484c/src/compiler/instruction.cc
[modify] https://crrev.com/5cda2db7d3ca954733a82cb203d46d2f6f73484c/src/ia32/assembler-ia32.h
[modify] https://crrev.com/5cda2db7d3ca954733a82cb203d46d2f6f73484c/src/mips/assembler-mips.h
[modify] https://crrev.com/5cda2db7d3ca954733a82cb203d46d2f6f73484c/src/mips64/assembler-mips64.h
[modify] https://crrev.com/5cda2db7d3ca954733a82cb203d46d2f6f73484c/src/ppc/assembler-ppc.h
[modify] https://crrev.com/5cda2db7d3ca954733a82cb203d46d2f6f73484c/src/s390/assembler-s390.h
[modify] https://crrev.com/5cda2db7d3ca954733a82cb203d46d2f6f73484c/src/x64/assembler-x64.h
[modify] https://crrev.com/5cda2db7d3ca954733a82cb203d46d2f6f73484c/src/x87/assembler-x87.h
[modify] https://crrev.com/5cda2db7d3ca954733a82cb203d46d2f6f73484c/test/cctest/compiler/test-gap-resolver.cc

Project Member

Comment 80 by bugdroid1@chromium.org, Jun 24 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/a933b7044a76d99c84607c846487590413cf6743

commit a933b7044a76d99c84607c846487590413cf6743
Author: bbudge <bbudge@chromium.org>
Date: Fri Jun 24 12:44:02 2016

[Turbofan] Add the concept of aliasing to RegisterConfiguration.
- Adds the concept of FP register aliasing to RegisterConfiguration.
- Changes RegisterAllocator to distinguish between FP representations
when allocating.
- Changes LinearScanAllocator to detect interference when FP register
aliasing is combining, as on ARM.
- Changes ARM code generation to allow all registers s0 - s31 to be
accessed.
- Adds unit tests for RegisterConfiguration, mostly to test aliasing
calculations.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2086653003
Cr-Commit-Position: refs/heads/master@{#37251}

[modify] https://crrev.com/a933b7044a76d99c84607c846487590413cf6743/src/compiler/arm/code-generator-arm.cc
[modify] https://crrev.com/a933b7044a76d99c84607c846487590413cf6743/src/compiler/instruction.cc
[modify] https://crrev.com/a933b7044a76d99c84607c846487590413cf6743/src/compiler/move-optimizer.cc
[modify] https://crrev.com/a933b7044a76d99c84607c846487590413cf6743/src/compiler/register-allocator-verifier.h
[modify] https://crrev.com/a933b7044a76d99c84607c846487590413cf6743/src/compiler/register-allocator.cc
[modify] https://crrev.com/a933b7044a76d99c84607c846487590413cf6743/src/compiler/register-allocator.h
[modify] https://crrev.com/a933b7044a76d99c84607c846487590413cf6743/src/compiler/wasm-linkage.cc
[modify] https://crrev.com/a933b7044a76d99c84607c846487590413cf6743/src/register-configuration.cc
[modify] https://crrev.com/a933b7044a76d99c84607c846487590413cf6743/src/register-configuration.h
[modify] https://crrev.com/a933b7044a76d99c84607c846487590413cf6743/test/cctest/compiler/test-run-native-calls.cc
[modify] https://crrev.com/a933b7044a76d99c84607c846487590413cf6743/test/unittests/compiler/instruction-sequence-unittest.cc
[add] https://crrev.com/a933b7044a76d99c84607c846487590413cf6743/test/unittests/register-configuration-unittest.cc
[modify] https://crrev.com/a933b7044a76d99c84607c846487590413cf6743/test/unittests/unittests.gyp

Project Member

Comment 81 by bugdroid1@chromium.org, Jun 27 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/a93f1bdb834b856fe87d338487cc966f151e8337

commit a93f1bdb834b856fe87d338487cc966f151e8337
Author: machenbach <machenbach@chromium.org>
Date: Mon Jun 27 08:01:52 2016

[test] Sync unittests gn build

Fix after:
https://codereview.chromium.org/2060743002/
https://codereview.chromium.org/2086653003/

BUG=v8:5086, v8:5092, v8:4124
TBR=bmeurer@chromium.org, yangguo@chromium.org,  bbudge@chromium.org

NOTRY=true

Review-Url: https://codereview.chromium.org/2095313002
Cr-Commit-Position: refs/heads/master@{#37274}

[modify] https://crrev.com/a93f1bdb834b856fe87d338487cc966f151e8337/test/unittests/BUILD.gn

Project Member

Comment 82 by bugdroid1@chromium.org, Jun 27 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/2db846d531878ef322b0dab6ffb4e394beb86fd6

commit 2db846d531878ef322b0dab6ffb4e394beb86fd6
Author: bbudge <bbudge@chromium.org>
Date: Mon Jun 27 11:38:58 2016

[arm] Eliminate OperandConverter Float32 and Float64 register methods.
Removes OperandConverter::*Float32* and *Float64* methods.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2091973002
Cr-Commit-Position: refs/heads/master@{#37285}

[modify] https://crrev.com/2db846d531878ef322b0dab6ffb4e394beb86fd6/src/compiler/arm/code-generator-arm.cc
[modify] https://crrev.com/2db846d531878ef322b0dab6ffb4e394beb86fd6/src/compiler/instruction.h

Project Member

Comment 83 by bugdroid1@chromium.org, Jun 27 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/5107f1c135afb081ab58e275cde48fe207e7db11

commit 5107f1c135afb081ab58e275cde48fe207e7db11
Author: bbudge <bbudge@chromium.org>
Date: Mon Jun 27 11:56:49 2016

[Turbofan] Allow compiler to elide complex aliasing code.
- Add a const bool kSimpleFPAliasing variable for each platform so it's
easier for the compiler to eliminate dead code.
- Modify RegisterAllocator to use it.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2101473002
Cr-Commit-Position: refs/heads/master@{#37288}

[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/src/arm/assembler-arm.h
[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/src/arm64/assembler-arm64.h
[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/src/compiler/register-allocator.cc
[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/src/compiler/register-allocator.h
[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/src/ia32/assembler-ia32.h
[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/src/mips/assembler-mips.h
[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/src/mips64/assembler-mips64.h
[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/src/ppc/assembler-ppc.h
[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/src/register-configuration.cc
[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/src/register-configuration.h
[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/src/s390/assembler-s390.h
[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/src/x64/assembler-x64.h
[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/src/x87/assembler-x87.h
[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/test/unittests/compiler/instruction-sequence-unittest.cc
[modify] https://crrev.com/5107f1c135afb081ab58e275cde48fe207e7db11/test/unittests/register-configuration-unittest.cc

Project Member

Comment 84 by bugdroid1@chromium.org, Jun 29 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/4b76dc85979094ac26499f2e527e422d4f0f6e58

commit 4b76dc85979094ac26499f2e527e422d4f0f6e58
Author: bbudge <bbudge@chromium.org>
Date: Wed Jun 29 11:47:06 2016

[Turbofan] Simplify operand canonicalization on archs with simple FP aliasing.
- Changes InstructionOperand canonicalization to map all FP operands to kFloat64 on Intel and other platforms with simple aliasing.
- Bypass expensive interference calculations and fixed FP live range processing for platforms with simple aliasing.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2101653003
Cr-Commit-Position: refs/heads/master@{#37388}

[modify] https://crrev.com/4b76dc85979094ac26499f2e527e422d4f0f6e58/src/compiler/instruction.cc
[modify] https://crrev.com/4b76dc85979094ac26499f2e527e422d4f0f6e58/src/compiler/instruction.h
[modify] https://crrev.com/4b76dc85979094ac26499f2e527e422d4f0f6e58/src/compiler/move-optimizer.cc
[modify] https://crrev.com/4b76dc85979094ac26499f2e527e422d4f0f6e58/src/compiler/register-allocator.cc

Project Member

Comment 85 by bugdroid1@chromium.org, Jun 29 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/cf62923e3ba3861d34a46381fb032c01ba42fb2f

commit cf62923e3ba3861d34a46381fb032c01ba42fb2f
Author: bbudge <bbudge@chromium.org>
Date: Wed Jun 29 22:40:43 2016

[Turbofan] Eliminate IsOutputRegisterOf and IsOutputFPRegisterOf checks.
- Eliminates tests for whether a fixed register needs to be preserved,
and conservatively adds a UsePosition for all fixed live ranges.

This speeds up ProcessInstructions, especially when ARM register
aliasing introduces fixed live ranges for float and SIMD 128 registers.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2103793003
Cr-Commit-Position: refs/heads/master@{#37408}

[modify] https://crrev.com/cf62923e3ba3861d34a46381fb032c01ba42fb2f/src/compiler/register-allocator.cc

Project Member

Comment 86 by bugdroid1@chromium.org, Jun 30 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89

commit aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89
Author: bbudge <bbudge@chromium.org>
Date: Thu Jun 30 11:29:20 2016

[Turbofan] Add Simd128 registers to RegisterConfiguration.
-Defines SIMD128_REGISTERS for all platforms.
-Adds Simd128 register information to RegisterConfiguration, and implements
aliasing calculations.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2092103004
Cr-Commit-Position: refs/heads/master@{#37437}

[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/arm/assembler-arm.h
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/arm64/assembler-arm64.h
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/compiler/move-optimizer.cc
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/compiler/register-allocator.cc
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/compiler/register-allocator.h
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/ia32/assembler-ia32.h
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/machine-type.h
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/mips/assembler-mips.h
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/mips64/assembler-mips64.h
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/ppc/assembler-ppc.h
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/register-configuration.cc
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/register-configuration.h
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/s390/assembler-s390.h
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/x64/assembler-x64.h
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/src/x87/assembler-x87.h
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/test/BUILD.gn
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/test/unittests/compiler/instruction-sequence-unittest.cc
[modify] https://crrev.com/aca3716a504c262ff8e5cd8b5ae7ba45d63b2e89/test/unittests/register-configuration-unittest.cc

Project Member

Comment 87 by bugdroid1@chromium.org, Jul 1 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/55841409c01f2c929f4e584cf77273346c006ad2

commit 55841409c01f2c929f4e584cf77273346c006ad2
Author: bbudge <bbudge@chromium.org>
Date: Fri Jul 01 00:56:00 2016

[Turbofan] Merge SpillRanges by byte_width rather than kind.
- Uses byte_width() to determine if spill ranges can be merged.
- Modifies InstructionOperand canonicalization to ignore representation for stack slots.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2074323002
Cr-Commit-Position: refs/heads/master@{#37463}

[modify] https://crrev.com/55841409c01f2c929f4e584cf77273346c006ad2/src/compiler/graph-visualizer.cc
[modify] https://crrev.com/55841409c01f2c929f4e584cf77273346c006ad2/src/compiler/instruction.h
[modify] https://crrev.com/55841409c01f2c929f4e584cf77273346c006ad2/src/compiler/register-allocator.cc
[modify] https://crrev.com/55841409c01f2c929f4e584cf77273346c006ad2/src/compiler/register-allocator.h

Project Member

Comment 88 by bugdroid1@chromium.org, Jul 1 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/26625644abe94bbc59331c3dd9178dad02c5c257

commit 26625644abe94bbc59331c3dd9178dad02c5c257
Author: bbudge <bbudge@chromium.org>
Date: Fri Jul 01 22:04:27 2016

[Turbofan] Add Simd128 regs to InstructionOperandConverter.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2117703003
Cr-Commit-Position: refs/heads/master@{#37483}

[modify] https://crrev.com/26625644abe94bbc59331c3dd9178dad02c5c257/src/compiler/code-generator-impl.h

Project Member

Comment 89 by bugdroid1@chromium.org, Jul 4 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/21b3c06e71f0e99e3285848db41a4664d8fd2838

commit 21b3c06e71f0e99e3285848db41a4664d8fd2838
Author: bbudge <bbudge@chromium.org>
Date: Mon Jul 04 12:30:53 2016

[Turbofan] Instruction::Print can handle SIMD 128 bit registers.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2116203002
Cr-Commit-Position: refs/heads/master@{#37498}

[modify] https://crrev.com/21b3c06e71f0e99e3285848db41a4664d8fd2838/src/compiler/instruction.cc

Project Member

Comment 93 by bugdroid1@chromium.org, Jul 12 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/3848099911e352346d2628f92f347acfd5ba23c7

commit 3848099911e352346d2628f92f347acfd5ba23c7
Author: bbudge <bbudge@chromium.org>
Date: Tue Jul 12 03:26:12 2016

[Turbofan] Add support for 16 byte frame slots.
AllocateSpillSlot can now handle requests for 16 byte slots.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2139663002
Cr-Commit-Position: refs/heads/master@{#37661}

[modify] https://crrev.com/3848099911e352346d2628f92f347acfd5ba23c7/src/compiler/frame.h
[modify] https://crrev.com/3848099911e352346d2628f92f347acfd5ba23c7/src/compiler/register-allocator.h

Project Member

Comment 94 by bugdroid1@chromium.org, Jul 12 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/0ddd158b7418c7819b6eb239a2d64181d6412aa1

commit 0ddd158b7418c7819b6eb239a2d64181d6412aa1
Author: bbudge <bbudge@chromium.org>
Date: Tue Jul 12 15:02:51 2016

[Turbofan] Register-register swap for x64 can use movapd instruction.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2144613002
Cr-Commit-Position: refs/heads/master@{#37684}

[modify] https://crrev.com/0ddd158b7418c7819b6eb239a2d64181d6412aa1/src/compiler/x64/code-generator-x64.cc

Project Member

Comment 95 by bugdroid1@chromium.org, Jul 13 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/26ecb4a1d775d506700d20542f723e8baeb37e48

commit 26ecb4a1d775d506700d20542f723e8baeb37e48
Author: bbudge <bbudge@chromium.org>
Date: Wed Jul 13 13:53:04 2016

[Turbofan] Add ia32 support for 4 and 16 byte moves and swaps.
- Adds move/swap handling for 4 and 16 bytes to ia32.
- Register allocator now only requests 4 bytes for floats on ia32 and arm.
- We probably need similar support in mips.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2027043002
Cr-Commit-Position: refs/heads/master@{#37714}

[modify] https://crrev.com/26ecb4a1d775d506700d20542f723e8baeb37e48/src/compiler/ia32/code-generator-ia32.cc
[modify] https://crrev.com/26ecb4a1d775d506700d20542f723e8baeb37e48/src/compiler/register-allocator.cc
[modify] https://crrev.com/26ecb4a1d775d506700d20542f723e8baeb37e48/src/ia32/assembler-ia32.cc
[modify] https://crrev.com/26ecb4a1d775d506700d20542f723e8baeb37e48/src/ia32/assembler-ia32.h
[modify] https://crrev.com/26ecb4a1d775d506700d20542f723e8baeb37e48/src/ia32/disasm-ia32.cc
[modify] https://crrev.com/26ecb4a1d775d506700d20542f723e8baeb37e48/test/cctest/test-disasm-ia32.cc

Project Member

Comment 96 by bugdroid1@chromium.org, Jul 13 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/a6ffe8efe1699ca06396c0885bd8272e45162987

commit a6ffe8efe1699ca06396c0885bd8272e45162987
Author: bbudge <bbudge@chromium.org>
Date: Wed Jul 13 23:00:37 2016

Revert of [Turbofan] Change AlignSavedCalleeRegisterSlots to AlignFrame. (patchset #2 id:20001 of https://codereview.chromium.org/2124983004/ )

Reason for revert:
Speculative revert to fix perf regression:
https://bugs.chromium.org/p/chromium/issues/detail?id=627803

Original issue's description:
> [Turbofan] Change AlignSavedCalleeRegisterSlots to AlignFrame.
> Clean up call sites.
>
> LOG=N
> BUG=v8:4124
>
> Committed: https://crrev.com/d8d75782fb90da21b92ca3dda59cfa3088ad3912
> Cr-Commit-Position: refs/heads/master@{#37650}

TBR=bmeurer@chromium.org,mtrofin@chromium.org,danno@chromium.org
# Not skipping CQ checks because original CL landed more than 1 days ago.
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2151563003
Cr-Commit-Position: refs/heads/master@{#37732}

[modify] https://crrev.com/a6ffe8efe1699ca06396c0885bd8272e45162987/src/compiler/arm/code-generator-arm.cc
[modify] https://crrev.com/a6ffe8efe1699ca06396c0885bd8272e45162987/src/compiler/frame.h
[modify] https://crrev.com/a6ffe8efe1699ca06396c0885bd8272e45162987/src/compiler/mips/code-generator-mips.cc
[modify] https://crrev.com/a6ffe8efe1699ca06396c0885bd8272e45162987/src/compiler/ppc/code-generator-ppc.cc
[modify] https://crrev.com/a6ffe8efe1699ca06396c0885bd8272e45162987/src/compiler/s390/code-generator-s390.cc
[modify] https://crrev.com/a6ffe8efe1699ca06396c0885bd8272e45162987/src/compiler/x64/code-generator-x64.cc

Project Member

Comment 97 by bugdroid1@chromium.org, Jul 15 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a

commit 73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a
Author: gdeepti <gdeepti@chromium.org>
Date: Fri Jul 15 08:29:05 2016

Convert SIMD machine ops to runtime function calls
 - Add Simd128 type to Wasm AST types
 - Add a pass that converts SIMD machine ops to runtime calls
 - Sample opcodes Int32x4Splat, Int32x4ExtractLane and test
 - Separate out generic SIMD Machine ops as these cannot be
 handled by runtime functions just yet.

LOG=N
BUG=v8:4124

R=bradnelson@chromium.org, bbudge@chromium.org, titzer@chromium.org

Review-Url: https://codereview.chromium.org/1991143002
Cr-Commit-Position: refs/heads/master@{#37789}

[modify] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/BUILD.gn
[add] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/src/compiler/simd-lowering.cc
[add] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/src/compiler/simd-lowering.h
[modify] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/src/compiler/wasm-compiler.cc
[modify] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/src/compiler/wasm-compiler.h
[modify] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/src/flag-definitions.h
[modify] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/src/v8.gyp
[modify] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/src/wasm/ast-decoder.cc
[modify] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/src/wasm/wasm-macro-gen.h
[modify] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/src/wasm/wasm-opcodes.cc
[modify] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/src/wasm/wasm-opcodes.h
[modify] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/test/cctest/cctest.gyp
[add] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/test/cctest/wasm/test-run-wasm-simd.cc
[modify] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/test/cctest/wasm/test-signatures.h
[add] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/test/mjsunit/wasm/test-wasm-simd-ops.js
[modify] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/test/mjsunit/wasm/wasm-constants.js

Project Member

Comment 98 by bugdroid1@chromium.org, Jul 15 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/9f46c1112b98e0e3e6317d244a76b96516b1ef16

commit 9f46c1112b98e0e3e6317d244a76b96516b1ef16
Author: machenbach <machenbach@chromium.org>
Date: Fri Jul 15 08:59:39 2016

Revert of Convert SIMD wasm ops to runtime function calls (patchset #17 id:320001 of https://codereview.chromium.org/1991143002/ )

Reason for revert:
[Sheriff] Violates msan and tsan:
https://build.chromium.org/p/client.v8/builders/V8%20Linux%20-%20arm64%20-%20sim%20-%20MSAN/builds/9663
https://build.chromium.org/p/client.v8/builders/V8%20Linux64%20TSAN/builds/10670

Original issue's description:
> Convert SIMD machine ops to runtime function calls
>  - Add Simd128 type to Wasm AST types
>  - Add a pass that converts SIMD machine ops to runtime calls
>  - Sample opcodes Int32x4Splat, Int32x4ExtractLane and test
>  - Separate out generic SIMD Machine ops as these cannot be
>  handled by runtime functions just yet.
>
> LOG=N
> BUG=v8:4124
>
> R=bradnelson@chromium.org, bbudge@chromium.org, titzer@chromium.org
>
> Committed: https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a
> Cr-Commit-Position: refs/heads/master@{#37789}

TBR=bbudge@chromium.org,bradnelson@chromium.org,titzer@chromium.org,gdeepti@chromium.org
# Skipping CQ checks because original CL landed less than 1 days ago.
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2154723002
Cr-Commit-Position: refs/heads/master@{#37790}

[modify] https://crrev.com/9f46c1112b98e0e3e6317d244a76b96516b1ef16/BUILD.gn
[delete] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/src/compiler/simd-lowering.cc
[delete] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/src/compiler/simd-lowering.h
[modify] https://crrev.com/9f46c1112b98e0e3e6317d244a76b96516b1ef16/src/compiler/wasm-compiler.cc
[modify] https://crrev.com/9f46c1112b98e0e3e6317d244a76b96516b1ef16/src/compiler/wasm-compiler.h
[modify] https://crrev.com/9f46c1112b98e0e3e6317d244a76b96516b1ef16/src/flag-definitions.h
[modify] https://crrev.com/9f46c1112b98e0e3e6317d244a76b96516b1ef16/src/v8.gyp
[modify] https://crrev.com/9f46c1112b98e0e3e6317d244a76b96516b1ef16/src/wasm/ast-decoder.cc
[modify] https://crrev.com/9f46c1112b98e0e3e6317d244a76b96516b1ef16/src/wasm/wasm-macro-gen.h
[modify] https://crrev.com/9f46c1112b98e0e3e6317d244a76b96516b1ef16/src/wasm/wasm-opcodes.cc
[modify] https://crrev.com/9f46c1112b98e0e3e6317d244a76b96516b1ef16/src/wasm/wasm-opcodes.h
[modify] https://crrev.com/9f46c1112b98e0e3e6317d244a76b96516b1ef16/test/cctest/cctest.gyp
[delete] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/test/cctest/wasm/test-run-wasm-simd.cc
[modify] https://crrev.com/9f46c1112b98e0e3e6317d244a76b96516b1ef16/test/cctest/wasm/test-signatures.h
[delete] https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a/test/mjsunit/wasm/test-wasm-simd-ops.js
[modify] https://crrev.com/9f46c1112b98e0e3e6317d244a76b96516b1ef16/test/mjsunit/wasm/wasm-constants.js

Project Member

Comment 99 by bugdroid1@chromium.org, Jul 16 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/18543ff1da34a7b12f583375b53320fcf5013931

commit 18543ff1da34a7b12f583375b53320fcf5013931
Author: gdeepti <gdeepti@chromium.org>
Date: Sat Jul 16 03:49:45 2016

Convert SIMD wasm ops to runtime function calls
 - Add Simd128 type to Wasm AST types
 - Decode SIMD prefix, wasm opcodes correctly
 - Add a pass that converts SIMD machine ops to runtime calls
 - Sample opcodes Int32x4Splat, Int32x4ExtractLane and test

LOG=N
BUG=v8:4124

R=bradnelson@chromium.org, bbudge@chromium.org, titzer@chromium.org

Committed: https://crrev.com/73df92fc2fdbbfadc17e8ab4e58ec56ae2b3d91a
Review-Url: https://codereview.chromium.org/1991143002
Cr-Original-Commit-Position: refs/heads/master@{#37789}
Cr-Commit-Position: refs/heads/master@{#37807}

[modify] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/BUILD.gn
[add] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/src/compiler/simd-lowering.cc
[add] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/src/compiler/simd-lowering.h
[modify] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/src/compiler/wasm-compiler.cc
[modify] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/src/compiler/wasm-compiler.h
[modify] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/src/flag-definitions.h
[modify] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/src/v8.gyp
[modify] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/src/wasm/ast-decoder.cc
[modify] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/src/wasm/wasm-macro-gen.h
[modify] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/src/wasm/wasm-opcodes.cc
[modify] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/src/wasm/wasm-opcodes.h
[modify] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/test/cctest/cctest.gyp
[add] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/test/cctest/wasm/test-run-wasm-simd.cc
[modify] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/test/cctest/wasm/test-signatures.h
[add] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/test/mjsunit/wasm/test-wasm-simd-ops.js
[modify] https://crrev.com/18543ff1da34a7b12f583375b53320fcf5013931/test/mjsunit/wasm/wasm-constants.js

Project Member

Comment 100 by bugdroid1@chromium.org, Jul 18 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/3266433462684761f54992162fc35a954e947d9b

commit 3266433462684761f54992162fc35a954e947d9b
Author: bbudge <bbudge@chromium.org>
Date: Mon Jul 18 11:06:05 2016

[Turbofan] Add simd128 fixed live ranges to inactive.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2157873002
Cr-Commit-Position: refs/heads/master@{#37829}

[modify] https://crrev.com/3266433462684761f54992162fc35a954e947d9b/src/compiler/register-allocator.cc

Project Member

Comment 102 by bugdroid1@chromium.org, Sep 9 2016

Labels: merge-merged-5.3
The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/8fbcbb4c7e20a66226c6128c122b37957533ef7e

commit 8fbcbb4c7e20a66226c6128c122b37957533ef7e
Author: hablich <hablich@chromium.org>
Date: Fri Sep 09 17:45:22 2016

Merged: [Turbofan] Simplify operand canonicalization on archs with simple FP aliasing. - Changes ...

Revision: 4b76dc85979094ac26499f2e527e422d4f0f6e58

BUG=v8:4124,chromium:644742
LOG=N
NOTRY=true
NOPRESUBMIT=true
NOTREECHECKS=true
R=bbudge@chromium.org

Review-Url: https://codereview.chromium.org/2316303007
Cr-Commit-Position: refs/branch-heads/5.3@{#67}
Cr-Branched-From: 820a23aade5e74a92d794e05a0c2b3597f0da4b5-refs/heads/5.3.332@{#2}
Cr-Branched-From: 37538cb2c1b4d75c41af386cb4fedbe5566f5608-refs/heads/master@{#37308}

[modify] https://crrev.com/8fbcbb4c7e20a66226c6128c122b37957533ef7e/src/compiler/instruction.cc
[modify] https://crrev.com/8fbcbb4c7e20a66226c6128c122b37957533ef7e/src/compiler/instruction.h
[modify] https://crrev.com/8fbcbb4c7e20a66226c6128c122b37957533ef7e/src/compiler/move-optimizer.cc
[modify] https://crrev.com/8fbcbb4c7e20a66226c6128c122b37957533ef7e/src/compiler/register-allocator.cc

Project Member

Comment 103 by bugdroid1@chromium.org, Sep 13 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/5d5efc662dd092e93b4611ee4b4445951ef999b4

commit 5d5efc662dd092e93b4611ee4b4445951ef999b4
Author: bbudge <bbudge@chromium.org>
Date: Tue Sep 13 16:16:20 2016

[Turbofan] Fix IsSlot function in MoveOptimizer.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2328423002
Cr-Commit-Position: refs/heads/master@{#39389}

[modify] https://crrev.com/5d5efc662dd092e93b4611ee4b4445951ef999b4/src/compiler/move-optimizer.cc

Project Member

Comment 104 by bugdroid1@chromium.org, Oct 3 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/b5c9e31c975e5a15fb93d4cc75d7ae7c36b43b4a

commit b5c9e31c975e5a15fb93d4cc75d7ae7c36b43b4a
Author: bbudge <bbudge@chromium.org>
Date: Mon Oct 03 21:39:25 2016

[Turbofan] Streamline InstructionOperand predicate methods.
- Orders machine representations so it's easier to check for floating
point.
- Orders operand types so it's easier to check for LocationOperands.
- Adds IsLocation, IsFPLocation predicates.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2382013003
Cr-Commit-Position: refs/heads/master@{#39941}

[modify] https://crrev.com/b5c9e31c975e5a15fb93d4cc75d7ae7c36b43b4a/src/compiler/instruction.h
[modify] https://crrev.com/b5c9e31c975e5a15fb93d4cc75d7ae7c36b43b4a/src/machine-type.h

Project Member

Comment 105 by bugdroid1@chromium.org, Oct 3 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/00ac990cc35850f36f67211faf6d8b722d7a7057

commit 00ac990cc35850f36f67211faf6d8b722d7a7057
Author: bbudge <bbudge@chromium.org>
Date: Mon Oct 03 23:45:51 2016

[Turbofan] Refactor GapResolver tests in preparation for FP aliasing.
- Changes tests to canonicalize FP slot/register moves, to simplify
testing any implementations that may fragment FP register moves.
- Adds code to generate correct ParallelMoves (e.g. no slot sources
of different reps overlapping.)
- Refactors test functions, so we can add manually generated tests
to current fuzzed tests.
- Adds SIMD operands, since these can be tested here now.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2365983002
Cr-Commit-Position: refs/heads/master@{#39943}

[modify] https://crrev.com/00ac990cc35850f36f67211faf6d8b722d7a7057/test/cctest/compiler/test-gap-resolver.cc

Project Member

Comment 106 by bugdroid1@chromium.org, Oct 10 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/5c4298a0ae825e699997eba21e1ebd52943e28b3

commit 5c4298a0ae825e699997eba21e1ebd52943e28b3
Author: bbudge <bbudge@chromium.org>
Date: Mon Oct 10 11:06:42 2016

[Turbofan] Allow FP operands and vregs in InstructionSequenceTest.
- Adds an optional representation field to VReg and TestOperand structs.
- Adds a simple FP allocation test to register-allocator-unittest.cc.
- Adds some simple FP tests to move-optimizer-unittest.cc.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2400513002
Cr-Commit-Position: refs/heads/master@{#40117}

[modify] https://crrev.com/5c4298a0ae825e699997eba21e1ebd52943e28b3/test/unittests/compiler/instruction-sequence-unittest.cc
[modify] https://crrev.com/5c4298a0ae825e699997eba21e1ebd52943e28b3/test/unittests/compiler/instruction-sequence-unittest.h
[modify] https://crrev.com/5c4298a0ae825e699997eba21e1ebd52943e28b3/test/unittests/compiler/move-optimizer-unittest.cc
[modify] https://crrev.com/5c4298a0ae825e699997eba21e1ebd52943e28b3/test/unittests/compiler/register-allocator-unittest.cc

Project Member

Comment 107 by bugdroid1@chromium.org, Oct 20 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/cf9ee0ec6c3768bf7f47363056169ce0624348ef

commit cf9ee0ec6c3768bf7f47363056169ce0624348ef
Author: aseemgarg <aseemgarg@chromium.org>
Date: Thu Oct 20 00:19:33 2016

[wasm] simd scalar lowering F32x4Add and I32x4Add

BUG=v8:4124
TEST:test-run-wasm-simd-lowering
R=titzer@chromium.org,bradnelson@chromium.org,gdeepti@chromium.org

Review-Url: https://chromiumcodereview.appspot.com/2294743003
Cr-Commit-Position: refs/heads/master@{#40448}

[modify] https://crrev.com/cf9ee0ec6c3768bf7f47363056169ce0624348ef/BUILD.gn
[add] https://crrev.com/cf9ee0ec6c3768bf7f47363056169ce0624348ef/src/compiler/simd-scalar-lowering.cc
[add] https://crrev.com/cf9ee0ec6c3768bf7f47363056169ce0624348ef/src/compiler/simd-scalar-lowering.h
[modify] https://crrev.com/cf9ee0ec6c3768bf7f47363056169ce0624348ef/src/compiler/wasm-compiler.cc
[modify] https://crrev.com/cf9ee0ec6c3768bf7f47363056169ce0624348ef/src/compiler/wasm-compiler.h
[modify] https://crrev.com/cf9ee0ec6c3768bf7f47363056169ce0624348ef/src/compiler/wasm-linkage.cc
[modify] https://crrev.com/cf9ee0ec6c3768bf7f47363056169ce0624348ef/src/v8.gyp
[modify] https://crrev.com/cf9ee0ec6c3768bf7f47363056169ce0624348ef/src/wasm/ast-decoder.cc
[modify] https://crrev.com/cf9ee0ec6c3768bf7f47363056169ce0624348ef/src/wasm/wasm-macro-gen.h
[modify] https://crrev.com/cf9ee0ec6c3768bf7f47363056169ce0624348ef/src/wasm/wasm-module.h
[modify] https://crrev.com/cf9ee0ec6c3768bf7f47363056169ce0624348ef/test/cctest/BUILD.gn
[modify] https://crrev.com/cf9ee0ec6c3768bf7f47363056169ce0624348ef/test/cctest/cctest.gyp
[add] https://crrev.com/cf9ee0ec6c3768bf7f47363056169ce0624348ef/test/cctest/wasm/test-run-wasm-simd-lowering.cc
[modify] https://crrev.com/cf9ee0ec6c3768bf7f47363056169ce0624348ef/test/cctest/wasm/wasm-run-utils.h

Project Member

Comment 108 by bugdroid1@chromium.org, Oct 26 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036

commit 09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036
Author: bbudge <bbudge@chromium.org>
Date: Wed Oct 26 16:04:11 2016

[Turbofan] Add concept of FP register aliasing on ARM 32.

- Modifies RegisterConfiguration to specify complex aliasing on ARM 32.
- Modifies RegisterAllocator to consider aliasing.
- Modifies ParallelMove::PrepareInsertAfter to handle aliasing.
- Modifies GapResolver to split wider register moves when interference
with smaller moves is detected.
- Modifies MoveOptimizer to handle aliasing.
- Adds ARM 32 macro-assembler pseudo move instructions to handle cases where
  split moves don't correspond to actual s-registers.
- Modifies CodeGenerator::AssembleMove and AssembleSwap to handle moves of
  different widths, and moves involving pseudo-s-registers.
- Adds unit tests for FP operand interference checking and PrepareInsertAfter.
- Adds more tests of FP for the move optimizer and register allocator.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2410673002
Cr-Commit-Position: refs/heads/master@{#40597}

[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/arm/macro-assembler-arm.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/arm/macro-assembler-arm.h
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/compiler/arm/code-generator-arm.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/compiler/gap-resolver.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/compiler/gap-resolver.h
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/compiler/instruction.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/compiler/instruction.h
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/compiler/move-optimizer.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/compiler/register-allocator.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/compiler/register-allocator.h
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/compiler/wasm-linkage.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/machine-type.h
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/register-configuration.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/register-configuration.h
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/src/zone/zone-allocator.h
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/test/cctest/compiler/test-gap-resolver.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/test/cctest/compiler/test-run-native-calls.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/test/unittests/BUILD.gn
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/test/unittests/compiler/instruction-sequence-unittest.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/test/unittests/compiler/instruction-sequence-unittest.h
[add] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/test/unittests/compiler/instruction-unittest.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/test/unittests/compiler/move-optimizer-unittest.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/test/unittests/compiler/register-allocator-unittest.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/test/unittests/register-configuration-unittest.cc
[modify] https://crrev.com/09ab8e6ad9440d15f3083a44ca0c1ab3ae84a036/test/unittests/unittests.gyp

Project Member

Comment 109 by bugdroid1@chromium.org, Oct 26 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/51bbfc7da258b21ecf448e7731bd8c2b89d3f43f

commit 51bbfc7da258b21ecf448e7731bd8c2b89d3f43f
Author: bbudge <bbudge@chromium.org>
Date: Wed Oct 26 17:28:26 2016

[Turbofan] Add USE for local used only by DCHECK.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2453813002
Cr-Commit-Position: refs/heads/master@{#40603}

[modify] https://crrev.com/51bbfc7da258b21ecf448e7731bd8c2b89d3f43f/src/compiler/register-allocator.cc

Project Member

Comment 110 by bugdroid1@chromium.org, Nov 2 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/d2c3ae774d9a14f1cd9ca8f1fa66d600049b5785

commit d2c3ae774d9a14f1cd9ca8f1fa66d600049b5785
Author: bbudge <bbudge@chromium.org>
Date: Wed Nov 02 09:53:48 2016

[Turbofan] Make fixed live ranges all double when aliasing is simple.
Only ARM should have fixed live range arrays for float / simd128.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2471533002
Cr-Commit-Position: refs/heads/master@{#40696}

[modify] https://crrev.com/d2c3ae774d9a14f1cd9ca8f1fa66d600049b5785/src/compiler/register-allocator.cc

Project Member

Comment 111 by bugdroid1@chromium.org, Nov 9 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/472cb045c5a809efa7572213362ef2c57b04946d

commit 472cb045c5a809efa7572213362ef2c57b04946d
Author: bbudge <bbudge@chromium.org>
Date: Wed Nov 09 18:48:53 2016

[Turbofan] Reduce register allocation work when we can.
- Track representations of virtual registers in InstructionSequence.
- Skip extra aliasing work when no floats or SIMD registers are used.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2468233004
Cr-Commit-Position: refs/heads/master@{#40870}

[modify] https://crrev.com/472cb045c5a809efa7572213362ef2c57b04946d/src/compiler/instruction.cc
[modify] https://crrev.com/472cb045c5a809efa7572213362ef2c57b04946d/src/compiler/instruction.h
[modify] https://crrev.com/472cb045c5a809efa7572213362ef2c57b04946d/src/compiler/register-allocator.cc
[modify] https://crrev.com/472cb045c5a809efa7572213362ef2c57b04946d/src/compiler/register-allocator.h
[modify] https://crrev.com/472cb045c5a809efa7572213362ef2c57b04946d/src/machine-type.h

Project Member

Comment 112 by bugdroid1@chromium.org, Nov 11 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/99c8144773bbde80bce17717807e6321715eddff

commit 99c8144773bbde80bce17717807e6321715eddff
Author: bbudge <bbudge@chromium.org>
Date: Fri Nov 11 19:53:25 2016

[Turbofan] CodeGenerator for ARM avoids moves from VFP to general regs.
- Adds VmovExtended, VswpExtended methods to MacroAssembler. These methods
use only VFP registers to perform s-register moves.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2497483002
Cr-Commit-Position: refs/heads/master@{#40939}

[modify] https://crrev.com/99c8144773bbde80bce17717807e6321715eddff/src/arm/macro-assembler-arm.cc
[modify] https://crrev.com/99c8144773bbde80bce17717807e6321715eddff/src/arm/macro-assembler-arm.h
[modify] https://crrev.com/99c8144773bbde80bce17717807e6321715eddff/src/compiler/arm/code-generator-arm.cc

Project Member

Comment 113 by bugdroid1@chromium.org, Nov 16 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/093267758ef4abe5b47688821b5ab5465eccb0d4

commit 093267758ef4abe5b47688821b5ab5465eccb0d4
Author: bbudge <bbudge@chromium.org>
Date: Wed Nov 16 15:00:41 2016

Revert of [Turbofan] CodeGenerator for ARM avoids moves from VFP to general regs. (patchset #4 id:60001 of https://codereview.chromium.org/2497483002/ )

Reason for revert:
This was a speculative fix for perf regressions on Nexus 10 and ChromeOS. However, perf graphs after this landed show no improvement, so we should go back to the smaller, simpler code before.

Original issue's description:
> [Turbofan] CodeGenerator for ARM avoids moves from VFP to general regs.
> - Adds VmovExtended, VswpExtended methods to MacroAssembler. These methods
> use only VFP registers to perform s-register moves.
>
> LOG=N
> BUG=v8:4124

TBR=bmeurer@chromium.org
# Not skipping CQ checks because original CL landed more than 1 days ago.
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2505003002
Cr-Commit-Position: refs/heads/master@{#41039}

[modify] https://crrev.com/093267758ef4abe5b47688821b5ab5465eccb0d4/src/arm/macro-assembler-arm.cc
[modify] https://crrev.com/093267758ef4abe5b47688821b5ab5465eccb0d4/src/arm/macro-assembler-arm.h
[modify] https://crrev.com/093267758ef4abe5b47688821b5ab5465eccb0d4/src/compiler/arm/code-generator-arm.cc

Project Member

Comment 114 by bugdroid1@chromium.org, Nov 23 2016

Labels: merge-merged-5.6
The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/bc24769bc2232a2eef1473002f6867e53dc246f1

commit bc24769bc2232a2eef1473002f6867e53dc246f1
Author: Michael Hablich <hablich@chromium.org>
Date: Wed Nov 23 16:47:39 2016

Merged: Revert of [Turbofan] CodeGenerator for ARM avoids moves from VFP to general regs. (patch ...

Revision: 093267758ef4abe5b47688821b5ab5465eccb0d4

BUG=v8:4124
LOG=N
NOTRY=true
NOPRESUBMIT=true
NOTREECHECKS=true
R=bbudge@chromium.org
TBR=bbudge@chromium.org

Review URL: https://codereview.chromium.org/2525023002 .

Cr-Commit-Position: refs/branch-heads/5.6@{#18}
Cr-Branched-From: bdd3886218dfe76e8560eb8a18401942452ae859-refs/heads/5.6.326@{#1}
Cr-Branched-From: 879f6599eee6e1dfcbe9a24bf688b261c03e9558-refs/heads/master@{#41014}

[modify] https://crrev.com/bc24769bc2232a2eef1473002f6867e53dc246f1/src/arm/macro-assembler-arm.cc
[modify] https://crrev.com/bc24769bc2232a2eef1473002f6867e53dc246f1/src/arm/macro-assembler-arm.h
[modify] https://crrev.com/bc24769bc2232a2eef1473002f6867e53dc246f1/src/compiler/arm/code-generator-arm.cc

Project Member

Comment 115 by bugdroid1@chromium.org, Nov 25 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/ef3f125d373d971c30efe53756507512e316a78a

commit ef3f125d373d971c30efe53756507512e316a78a
Author: bbudge <bbudge@chromium.org>
Date: Fri Nov 25 19:36:45 2016

[Turbofan] Add ARM support for simd128 moves and swaps.
- Adds vmov, vswp instructions for QwNeonRegisters.
- Refactors existing vswp implementation, moves non-Neon adaption to
MacroAssembler.
- Adds simd128 support to CodeGenerator AssembleMove, AssembleSwap.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2523933002
Cr-Commit-Position: refs/heads/master@{#41291}

[modify] https://crrev.com/ef3f125d373d971c30efe53756507512e316a78a/src/arm/assembler-arm.cc
[modify] https://crrev.com/ef3f125d373d971c30efe53756507512e316a78a/src/arm/assembler-arm.h
[modify] https://crrev.com/ef3f125d373d971c30efe53756507512e316a78a/src/arm/constants-arm.h
[modify] https://crrev.com/ef3f125d373d971c30efe53756507512e316a78a/src/arm/disasm-arm.cc
[modify] https://crrev.com/ef3f125d373d971c30efe53756507512e316a78a/src/arm/macro-assembler-arm.cc
[modify] https://crrev.com/ef3f125d373d971c30efe53756507512e316a78a/src/arm/macro-assembler-arm.h
[modify] https://crrev.com/ef3f125d373d971c30efe53756507512e316a78a/src/arm/simulator-arm.cc
[modify] https://crrev.com/ef3f125d373d971c30efe53756507512e316a78a/src/compiler/arm/code-generator-arm.cc
[modify] https://crrev.com/ef3f125d373d971c30efe53756507512e316a78a/test/cctest/test-assembler-arm.cc
[modify] https://crrev.com/ef3f125d373d971c30efe53756507512e316a78a/test/cctest/test-disasm-arm.cc

Project Member

Comment 116 by bugdroid1@chromium.org, Dec 1 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/df9deb5381dbf6e87e659bbad95e8b791b423554

commit df9deb5381dbf6e87e659bbad95e8b791b423554
Author: bbudge <bbudge@chromium.org>
Date: Thu Dec 01 19:53:06 2016

[Turbofan] Canonicalize SIMD 32x4 Select, Swizzle, and Shuffle.
- These operations are identical for Float32x4 and Int32x4.
- Make them generic, following the naming for generic Simd128 / S128
opcodes.
- F32x4/I32x4 -> S32x4, similarly to S128
- Float32x4/Int32x4 -> Simd32x4, similarly to Simd128.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2543773002
Cr-Commit-Position: refs/heads/master@{#41437}

[modify] https://crrev.com/df9deb5381dbf6e87e659bbad95e8b791b423554/src/compiler/instruction-selector.h
[modify] https://crrev.com/df9deb5381dbf6e87e659bbad95e8b791b423554/src/compiler/machine-operator.cc
[modify] https://crrev.com/df9deb5381dbf6e87e659bbad95e8b791b423554/src/compiler/machine-operator.h
[modify] https://crrev.com/df9deb5381dbf6e87e659bbad95e8b791b423554/src/compiler/opcodes.h
[modify] https://crrev.com/df9deb5381dbf6e87e659bbad95e8b791b423554/src/wasm/wasm-opcodes.h

Project Member

Comment 117 by bugdroid1@chromium.org, Dec 2 2016

Project Member

Comment 118 by bugdroid1@chromium.org, Dec 15 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/03f33f2e68641903a982a025b0ba645c8ba9f9b3

commit 03f33f2e68641903a982a025b0ba645c8ba9f9b3
Author: bbudge <bbudge@chromium.org>
Date: Thu Dec 15 18:15:23 2016

[Turbofan] Add ARM NEON instructions for implementing SIMD.
- Adds NEON instructions to assembler, disassembler, simulator.
- Adds ExtractLane, ReplaceLane functions to macro assembler.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2546933002
Cr-Commit-Position: refs/heads/master@{#41737}

[modify] https://crrev.com/03f33f2e68641903a982a025b0ba645c8ba9f9b3/src/arm/assembler-arm.cc
[modify] https://crrev.com/03f33f2e68641903a982a025b0ba645c8ba9f9b3/src/arm/assembler-arm.h
[modify] https://crrev.com/03f33f2e68641903a982a025b0ba645c8ba9f9b3/src/arm/constants-arm.h
[modify] https://crrev.com/03f33f2e68641903a982a025b0ba645c8ba9f9b3/src/arm/disasm-arm.cc
[modify] https://crrev.com/03f33f2e68641903a982a025b0ba645c8ba9f9b3/src/arm/macro-assembler-arm.cc
[modify] https://crrev.com/03f33f2e68641903a982a025b0ba645c8ba9f9b3/src/arm/macro-assembler-arm.h
[modify] https://crrev.com/03f33f2e68641903a982a025b0ba645c8ba9f9b3/src/arm/simulator-arm.cc
[modify] https://crrev.com/03f33f2e68641903a982a025b0ba645c8ba9f9b3/src/arm/simulator-arm.h
[modify] https://crrev.com/03f33f2e68641903a982a025b0ba645c8ba9f9b3/test/cctest/test-assembler-arm.cc
[modify] https://crrev.com/03f33f2e68641903a982a025b0ba645c8ba9f9b3/test/cctest/test-disasm-arm.cc
[modify] https://crrev.com/03f33f2e68641903a982a025b0ba645c8ba9f9b3/test/cctest/test-macro-assembler-arm.cc

Project Member

Comment 119 by bugdroid1@chromium.org, Dec 17 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/431223f34fafec07b7c42f6fa2fb832b82d86c94

commit 431223f34fafec07b7c42f6fa2fb832b82d86c94
Author: bbudge <bbudge@chromium.org>
Date: Sat Dec 17 21:56:26 2016

[ARM] Add NEON instructions for implementing SIMD.
- Adds vabs, vneg, vmul, vext, vzip, vrev instructions.
- Adds Swizzle function to macro assembler.
- Simplifies if-else logic in disassembler, simulator, for Neon special.
- Some refactoring of Neon assembler, macro-assembler tests.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2579913002
Cr-Commit-Position: refs/heads/master@{#41781}

[modify] https://crrev.com/431223f34fafec07b7c42f6fa2fb832b82d86c94/src/arm/assembler-arm.cc
[modify] https://crrev.com/431223f34fafec07b7c42f6fa2fb832b82d86c94/src/arm/assembler-arm.h
[modify] https://crrev.com/431223f34fafec07b7c42f6fa2fb832b82d86c94/src/arm/disasm-arm.cc
[modify] https://crrev.com/431223f34fafec07b7c42f6fa2fb832b82d86c94/src/arm/macro-assembler-arm.cc
[modify] https://crrev.com/431223f34fafec07b7c42f6fa2fb832b82d86c94/src/arm/macro-assembler-arm.h
[modify] https://crrev.com/431223f34fafec07b7c42f6fa2fb832b82d86c94/src/arm/simulator-arm.cc
[modify] https://crrev.com/431223f34fafec07b7c42f6fa2fb832b82d86c94/test/cctest/test-assembler-arm.cc
[modify] https://crrev.com/431223f34fafec07b7c42f6fa2fb832b82d86c94/test/cctest/test-disasm-arm.cc
[modify] https://crrev.com/431223f34fafec07b7c42f6fa2fb832b82d86c94/test/cctest/test-macro-assembler-arm.cc

Project Member

Comment 120 by bugdroid1@chromium.org, Dec 19 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/0625a686b5971b36b0116ec5c8cebf4428689cb4

commit 0625a686b5971b36b0116ec5c8cebf4428689cb4
Author: bbudge <bbudge@chromium.org>
Date: Mon Dec 19 22:23:03 2016

[Turbofan] Add native ARM support for basic SIMD 32x4 operations.
- Adds Float32x4 ExtractLane, ReplaceLane, Splat, Add, Sub,
and conversions to Int32x4 and Uint32x4.
- Adds Int32x4 ExtractLane, ReplaceLane, Splat, Add, Sub and
conversions to Float32x4 (int and unsigned int).
- Adds Int32x4 CompareEqual, CompareNotEqual.
- Adds S32x4 Select.
- Adds tests for all new SIMD operations.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2584863002
Cr-Commit-Position: refs/heads/master@{#41828}

[modify] https://crrev.com/0625a686b5971b36b0116ec5c8cebf4428689cb4/src/arm/assembler-arm-inl.h
[modify] https://crrev.com/0625a686b5971b36b0116ec5c8cebf4428689cb4/src/arm/simulator-arm.cc
[modify] https://crrev.com/0625a686b5971b36b0116ec5c8cebf4428689cb4/src/compiler/arm/code-generator-arm.cc
[modify] https://crrev.com/0625a686b5971b36b0116ec5c8cebf4428689cb4/src/compiler/arm/instruction-codes-arm.h
[modify] https://crrev.com/0625a686b5971b36b0116ec5c8cebf4428689cb4/src/compiler/arm/instruction-scheduler-arm.cc
[modify] https://crrev.com/0625a686b5971b36b0116ec5c8cebf4428689cb4/src/compiler/arm/instruction-selector-arm.cc
[modify] https://crrev.com/0625a686b5971b36b0116ec5c8cebf4428689cb4/src/compiler/instruction-selector.cc
[modify] https://crrev.com/0625a686b5971b36b0116ec5c8cebf4428689cb4/src/compiler/wasm-compiler.cc
[modify] https://crrev.com/0625a686b5971b36b0116ec5c8cebf4428689cb4/src/wasm/wasm-macro-gen.h
[modify] https://crrev.com/0625a686b5971b36b0116ec5c8cebf4428689cb4/src/wasm/wasm-opcodes.h
[modify] https://crrev.com/0625a686b5971b36b0116ec5c8cebf4428689cb4/test/cctest/BUILD.gn
[modify] https://crrev.com/0625a686b5971b36b0116ec5c8cebf4428689cb4/test/cctest/wasm/test-run-wasm-simd.cc

Project Member

Comment 123 by bugdroid1@chromium.org, Dec 21 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/7a6138ae11b7e1108bb3ced923993a3dc2def4eb

commit 7a6138ae11b7e1108bb3ced923993a3dc2def4eb
Author: bbudge <bbudge@chromium.org>
Date: Wed Dec 21 15:31:42 2016

[WASM] Skip SIMD test values that may result in denormalized numbers.
On ARM Neon at least, denormals flush to zero, which may not match
regular FP behavior.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2598583002
Cr-Commit-Position: refs/heads/master@{#41895}

[modify] https://crrev.com/7a6138ae11b7e1108bb3ced923993a3dc2def4eb/test/cctest/wasm/test-run-wasm-simd.cc

Project Member

Comment 124 by bugdroid1@chromium.org, Dec 22 2016

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/0f12793f69992c122f8ef06b670d089230e03a41

commit 0f12793f69992c122f8ef06b670d089230e03a41
Author: bbudge <bbudge@chromium.org>
Date: Thu Dec 22 16:05:05 2016

[WASM] Skip failing F32x4 tests on ARM.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2589283002
Cr-Commit-Position: refs/heads/master@{#41925}

[modify] https://crrev.com/0f12793f69992c122f8ef06b670d089230e03a41/test/cctest/cctest.status

Project Member

Comment 125 by bugdroid1@chromium.org, Jan 9 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/ab14a1360104b815470cc06a5b600a057de6d5be

commit ab14a1360104b815470cc06a5b600a057de6d5be
Author: bbudge <bbudge@chromium.org>
Date: Mon Jan 09 23:10:06 2017

[ARM] Add get_q_register, set_q_register overloads for NEON instructions.
Adds overloads for float, int32, int16, uint16, int8 and uint8 arrays.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2619223002
Cr-Commit-Position: refs/heads/master@{#42153}

[modify] https://crrev.com/ab14a1360104b815470cc06a5b600a057de6d5be/src/arm/simulator-arm.cc
[modify] https://crrev.com/ab14a1360104b815470cc06a5b600a057de6d5be/src/arm/simulator-arm.h

Project Member

Comment 126 by bugdroid1@chromium.org, Jan 9 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/5560bbb498252334595a39bb5f313ac8eb82cfe1

commit 5560bbb498252334595a39bb5f313ac8eb82cfe1
Author: bbudge <bbudge@chromium.org>
Date: Mon Jan 09 23:11:17 2017

[WASM] Fix failing Wasm SIMD F32x4 tests.
- Perform lane checks using FP compare instead of reinterpret casts. 0 and -0
will be different under I32 compare.
- Some arithmetic operations can generate NaN results, such as adding -Inf
and +Inf. Skip these tests until we have a way to do more sophisticated
FP comparisons in the SIMD tests.
- Eliminate a redundant F32x4 parameter for FP SIMD vector checking. We will only have this one FP type.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2594043002
Cr-Commit-Position: refs/heads/master@{#42154}

[modify] https://crrev.com/5560bbb498252334595a39bb5f313ac8eb82cfe1/test/cctest/cctest.status
[modify] https://crrev.com/5560bbb498252334595a39bb5f313ac8eb82cfe1/test/cctest/wasm/test-run-wasm-simd.cc

Project Member

Comment 127 by bugdroid1@chromium.org, Jan 10 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/0df234b0edb49fa83e8b7b5464d3340f8ac27fd9

commit 0df234b0edb49fa83e8b7b5464d3340f8ac27fd9
Author: bbudge <bbudge@chromium.org>
Date: Tue Jan 10 09:34:32 2017

Revert of [WASM] Fix failing Wasm SIMD F32x4 tests. (patchset #7 id:130001 of https://codereview.chromium.org/2594043002/ )

Reason for revert:
F32x4Add / Sub are still failing. I'll have to investigate on ARM hardware when I get back.

Original issue's description:
> [WASM] Fix failing Wasm SIMD F32x4 tests.
> - Perform lane checks using FP compare instead of reinterpret casts. 0 and -0
> will be different under I32 compare.
> - Some arithmetic operations can generate NaN results, such as adding -Inf
> and +Inf. Skip these tests until we have a way to do more sophisticated
> FP comparisons in the SIMD tests.
> - Eliminate a redundant F32x4 parameter for FP SIMD vector checking. We will only have this one FP type.
>
> LOG=N
> BUG=v8:4124
>
> Review-Url: https://codereview.chromium.org/2594043002
> Cr-Commit-Position: refs/heads/master@{#42154}
> Committed: https://chromium.googlesource.com/v8/v8/+/5560bbb498252334595a39bb5f313ac8eb82cfe1

TBR=titzer@chromium.org
# Skipping CQ checks because original CL landed less than 1 days ago.
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2624713002
Cr-Commit-Position: refs/heads/master@{#42162}

[modify] https://crrev.com/0df234b0edb49fa83e8b7b5464d3340f8ac27fd9/test/cctest/cctest.status
[modify] https://crrev.com/0df234b0edb49fa83e8b7b5464d3340f8ac27fd9/test/cctest/wasm/test-run-wasm-simd.cc

Project Member

Comment 131 by bugdroid1@chromium.org, Jan 13 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/497a7e4254cda8f5b0013c1545e8884bcc527068

commit 497a7e4254cda8f5b0013c1545e8884bcc527068
Author: bbudge <bbudge@chromium.org>
Date: Fri Jan 13 12:03:23 2017

[ARM] Add tolerance to vrecpe, vrsqrte instruction tests.
The simulator implements these exactly, but on ARM hardware,
the estimates are not exact, so CHECK_EQ will fail. This CL adds
a tolerance to the checks.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2628153003
Cr-Commit-Position: refs/heads/master@{#42320}

[modify] https://crrev.com/497a7e4254cda8f5b0013c1545e8884bcc527068/test/cctest/test-assembler-arm.cc

Project Member

Comment 132 by bugdroid1@chromium.org, Jan 16 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/a7e67924d1e52c649a5f4debba3232f2fd9af439

commit a7e67924d1e52c649a5f4debba3232f2fd9af439
Author: bbudge <bbudge@chromium.org>
Date: Mon Jan 16 19:36:25 2017

[ARM] Add vmin, vmax NEON instructions.
- Adds vmin, vmax for FP and integer vectors, both signed and unsigned.
- Regularizes switching logic in disasm and simulator for special codes
4 and 6.
- Factors vrecpe, vrsqrte, vrecps, vrsqrts into helper fns.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2623993006
Cr-Commit-Position: refs/heads/master@{#42385}

[modify] https://crrev.com/a7e67924d1e52c649a5f4debba3232f2fd9af439/src/arm/assembler-arm.cc
[modify] https://crrev.com/a7e67924d1e52c649a5f4debba3232f2fd9af439/src/arm/assembler-arm.h
[modify] https://crrev.com/a7e67924d1e52c649a5f4debba3232f2fd9af439/src/arm/disasm-arm.cc
[modify] https://crrev.com/a7e67924d1e52c649a5f4debba3232f2fd9af439/src/arm/simulator-arm.cc
[modify] https://crrev.com/a7e67924d1e52c649a5f4debba3232f2fd9af439/test/cctest/test-assembler-arm.cc
[modify] https://crrev.com/a7e67924d1e52c649a5f4debba3232f2fd9af439/test/cctest/test-disasm-arm.cc

Project Member

Comment 133 by bugdroid1@chromium.org, Jan 18 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/ac620154eeb042f17e9e35abb6b93635f89bf51f

commit ac620154eeb042f17e9e35abb6b93635f89bf51f
Author: bbudge <bbudge@chromium.org>
Date: Wed Jan 18 15:11:35 2017

[ARM] Refactor NEON binary ops in assembler.
- Refactors many FP, integer, and signed integer instructions where
possible.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2639443002
Cr-Commit-Position: refs/heads/master@{#42463}

[modify] https://crrev.com/ac620154eeb042f17e9e35abb6b93635f89bf51f/src/arm/assembler-arm.cc
[modify] https://crrev.com/ac620154eeb042f17e9e35abb6b93635f89bf51f/src/arm/assembler-arm.h
[modify] https://crrev.com/ac620154eeb042f17e9e35abb6b93635f89bf51f/src/arm/constants-arm.h
[modify] https://crrev.com/ac620154eeb042f17e9e35abb6b93635f89bf51f/src/arm/macro-assembler-arm.cc

Project Member

Comment 135 by bugdroid1@chromium.org, Jan 26 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c

commit c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c
Author: bbudge <bbudge@chromium.org>
Date: Thu Jan 26 02:18:00 2017

[Turbofan] Add other integer SIMD types, add more integer ops.
- Adds Int16x8, Int8x16 types.
- Adds neg, abs unary ops.
- Adds add, sub, mul, and signed / unsigned min / max, comparison ops.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2638133002
Cr-Commit-Position: refs/heads/master@{#42674}

[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/src/compiler/arm/code-generator-arm.cc
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/src/compiler/arm/instruction-codes-arm.h
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/src/compiler/arm/instruction-scheduler-arm.cc
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/src/compiler/arm/instruction-selector-arm.cc
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/src/compiler/common-operator.cc
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/src/compiler/common-operator.h
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/src/compiler/graph.h
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/src/compiler/instruction-selector.cc
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/src/compiler/machine-graph-verifier.cc
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/src/compiler/machine-operator.cc
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/src/compiler/machine-operator.h
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/src/compiler/wasm-compiler.cc
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/src/wasm/function-body-decoder.cc
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/src/wasm/wasm-macro-gen.h
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/test/cctest/compiler/value-helper.h
[modify] https://crrev.com/c5bdbbbebe12ba41e69f5e4cddc443ede2f7576c/test/cctest/wasm/test-run-wasm-simd.cc

Project Member

Comment 136 by bugdroid1@chromium.org, Jan 31 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/c0b1bcba2f33565201eaf3148b10dbe5d4c9231a

commit c0b1bcba2f33565201eaf3148b10dbe5d4c9231a
Author: bbudge <bbudge@chromium.org>
Date: Tue Jan 31 01:34:04 2017

[ARM] Macro-ize SIMD visitors in InstructionSelector.
- Uses macros for splat, extract lane, replace lane, unary
ops and binary ops.
- Renames ARM SIMD instruction codes to match machine
operator names.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2652893013
Cr-Commit-Position: refs/heads/master@{#42799}

[modify] https://crrev.com/c0b1bcba2f33565201eaf3148b10dbe5d4c9231a/src/compiler/arm/code-generator-arm.cc
[modify] https://crrev.com/c0b1bcba2f33565201eaf3148b10dbe5d4c9231a/src/compiler/arm/instruction-codes-arm.h
[modify] https://crrev.com/c0b1bcba2f33565201eaf3148b10dbe5d4c9231a/src/compiler/arm/instruction-scheduler-arm.cc
[modify] https://crrev.com/c0b1bcba2f33565201eaf3148b10dbe5d4c9231a/src/compiler/arm/instruction-selector-arm.cc

Project Member

Comment 137 by bugdroid1@chromium.org, Feb 1 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/d8ab932ceb3b906f36ab3216f84d8e626b3e5a5e

commit d8ab932ceb3b906f36ab3216f84d8e626b3e5a5e
Author: bbudge <bbudge@chromium.org>
Date: Wed Feb 01 17:02:57 2017

[Turbofan] Macro-ize instruction selection for x64.
- Uses macros to reduce code duplication.
- Uses calls to VisitRO and VisitRR to reduce code bloat.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2668753004
Cr-Original-Commit-Position: refs/heads/master@{#42828}
Committed: https://chromium.googlesource.com/v8/v8/+/e8e2e3c826d42490f809e1c45750bbb438b60d8c
Review-Url: https://codereview.chromium.org/2668753004
Cr-Commit-Position: refs/heads/master@{#42862}

[modify] https://crrev.com/d8ab932ceb3b906f36ab3216f84d8e626b3e5a5e/src/compiler/x64/instruction-selector-x64.cc

Project Member

Comment 139 by bugdroid1@chromium.org, Feb 1 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/6a82fe90684b16f885fe33bbf37e5c7f68dcbcf9

commit 6a82fe90684b16f885fe33bbf37e5c7f68dcbcf9
Author: bbudge <bbudge@chromium.org>
Date: Wed Feb 01 21:37:35 2017

[Turbofan] Macro-ize instruction selection for ia32.
- Uses macros to reduce code duplication.
- Uses calls to VisitRO, VisitRR, VisitRROFloat, and VisitFloatUnop to
  reduce code bloat.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2669683002
Cr-Original-Commit-Position: refs/heads/master@{#42830}
Committed: https://chromium.googlesource.com/v8/v8/+/5e6eb91d0d66c9a118f1cc576accb649a17c5a9d
Review-Url: https://codereview.chromium.org/2669683002
Cr-Commit-Position: refs/heads/master@{#42870}

[modify] https://crrev.com/6a82fe90684b16f885fe33bbf37e5c7f68dcbcf9/src/compiler/ia32/instruction-selector-ia32.cc

Project Member

Comment 140 by bugdroid1@chromium.org, Feb 7 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/04568c52161afaf71569ba7fe25288c3dbf041cb

commit 04568c52161afaf71569ba7fe25288c3dbf041cb
Author: bbudge <bbudge@chromium.org>
Date: Tue Feb 07 17:33:37 2017

[Turbofan] Add more integer SIMD operations for ARM.
- Adds logical and arithmetic shifts for all integer types.
- Adds min and max for all integer types.
- Adds saturating add and subtract for small integer types.
- Removes lane operations from the MachineOperatorCache.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2668013003
Cr-Commit-Position: refs/heads/master@{#43005}

[modify] https://crrev.com/04568c52161afaf71569ba7fe25288c3dbf041cb/src/compiler/arm/code-generator-arm.cc
[modify] https://crrev.com/04568c52161afaf71569ba7fe25288c3dbf041cb/src/compiler/arm/instruction-codes-arm.h
[modify] https://crrev.com/04568c52161afaf71569ba7fe25288c3dbf041cb/src/compiler/arm/instruction-scheduler-arm.cc
[modify] https://crrev.com/04568c52161afaf71569ba7fe25288c3dbf041cb/src/compiler/arm/instruction-selector-arm.cc
[modify] https://crrev.com/04568c52161afaf71569ba7fe25288c3dbf041cb/src/compiler/code-generator-impl.h
[modify] https://crrev.com/04568c52161afaf71569ba7fe25288c3dbf041cb/src/compiler/instruction-selector.cc
[modify] https://crrev.com/04568c52161afaf71569ba7fe25288c3dbf041cb/src/compiler/machine-operator.cc
[modify] https://crrev.com/04568c52161afaf71569ba7fe25288c3dbf041cb/src/compiler/machine-operator.h
[modify] https://crrev.com/04568c52161afaf71569ba7fe25288c3dbf041cb/src/compiler/wasm-compiler.cc
[modify] https://crrev.com/04568c52161afaf71569ba7fe25288c3dbf041cb/src/compiler/wasm-compiler.h
[modify] https://crrev.com/04568c52161afaf71569ba7fe25288c3dbf041cb/src/wasm/function-body-decoder.cc
[modify] https://crrev.com/04568c52161afaf71569ba7fe25288c3dbf041cb/src/wasm/wasm-macro-gen.h
[modify] https://crrev.com/04568c52161afaf71569ba7fe25288c3dbf041cb/src/wasm/wasm-opcodes.h
[modify] https://crrev.com/04568c52161afaf71569ba7fe25288c3dbf041cb/test/cctest/wasm/test-run-wasm-simd.cc

Project Member

Comment 141 by bugdroid1@chromium.org, Feb 13 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/d170c57ab996d00c4665a9d865bd5754a1806c6c

commit d170c57ab996d00c4665a9d865bd5754a1806c6c
Author: bbudge <bbudge@chromium.org>
Date: Mon Feb 13 15:59:22 2017

Remove SIMD.js from V8.

LOG=Y
BUG=v8:4124,5948
R=bradnelson@chromium.org,bmeurer@chromium.org,jochen@chromium.org,hpayer@chromium.org,danno@chromium.org
(notry since trybots can't patch directory deletes)
NOTRY=true

Review-Url: https://codereview.chromium.org/2684313003
Cr-Commit-Position: refs/heads/master@{#43162}

[modify] https://crrev.com/d170c57ab996d00c4665a9d865bd5754a1806c6c/.gitignore
[modify] https://crrev.com/d170c57ab996d00c4665a9d865bd5754a1806c6c/BUILD.gn
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[modify] https://crrev.com/d170c57ab996d00c4665a9d865bd5754a1806c6c/include/v8-profiler.h
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Project Member

Comment 142 by bugdroid1@chromium.org, Feb 13 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/43fc15bb795a203a01f409ed1f0dcada7a38f295

commit 43fc15bb795a203a01f409ed1f0dcada7a38f295
Author: bradnelson <bradnelson@chromium.org>
Date: Mon Feb 13 18:12:14 2017

Revert of Remove SIMD.js from V8. (patchset #7 id:120001 of https://codereview.chromium.org/2684313003/ )

Reason for revert:
red

Original issue's description:
> Remove SIMD.js from V8.
>
> LOG=Y
> BUG=v8:4124,5948
> R=bradnelson@chromium.org,bmeurer@chromium.org,jochen@chromium.org,hpayer@chromium.org,danno@chromium.org
> (notry since trybots can't patch directory deletes)
> NOTRY=true
>
> Review-Url: https://codereview.chromium.org/2684313003
> Cr-Commit-Position: refs/heads/master@{#43162}
> Committed: https://chromium.googlesource.com/v8/v8/+/d170c57ab996d00c4665a9d865bd5754a1806c6c

TBR=bmeurer@chromium.org,jochen@chromium.org,hpayer@chromium.org,danno@chromium.org,bradnelson@google.com,bbudge@chromium.org
# Skipping CQ checks because original CL landed less than 1 days ago.
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true
BUG=v8:4124,5948

Review-Url: https://codereview.chromium.org/2692933002
Cr-Commit-Position: refs/heads/master@{#43164}

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Project Member

Comment 143 by bugdroid1@chromium.org, Feb 13 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/chromium/tools/build/+/d1ea2270109e4a5f409d845a13da30528733e513

commit d1ea2270109e4a5f409d845a13da30528733e513
Author: Michael Achenbach <machenbach@chromium.org>
Date: Mon Feb 13 19:57:58 2017

V8: Remove simdjs testing

BUG=v8:4124
TBR=bradnelson@chromium.org,bbudge@chromium.org,tandrii@chromium.org

Change-Id: I53fce345e28edba80d1d6b04a2cf6496840fad10
Reviewed-on: https://chromium-review.googlesource.com/441826
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Commit-Queue: Michael Achenbach <machenbach@chromium.org>

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Project Member

Comment 144 by bugdroid1@chromium.org, Feb 13 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/11f88ef53f8e7c5aecfccd52e2a076a73efd413a

commit 11f88ef53f8e7c5aecfccd52e2a076a73efd413a
Author: bbudge <bbudge@chromium.org>
Date: Mon Feb 13 20:24:43 2017

[Turbofan] Add more non-arithmetic SIMD operations.
- Renames select, swizzle, and shuffle to be consistent with the S128 and
  existing S32x4 ops, and reflect that these aren't arithmetic.
  e.g. I16x8Swizzle -> S16x8Swizzle.
- Implements S16x8 and S8x16 Select operations and tests.
- Implements S128And, Or, Xor, Not operations and tests.
- Implements Swizzle for 32x4 formats.
- Refactors test macros that generate SIMD code.

TEST=cctest/test-run-wasm-simd/*

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2683713003
Cr-Commit-Position: refs/heads/master@{#43168}

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Project Member

Comment 145 by bugdroid1@chromium.org, Feb 13 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/a9b59a11f1bfe069afabe5567f919727456f1f12

commit a9b59a11f1bfe069afabe5567f919727456f1f12
Author: bbudge <bbudge@chromium.org>
Date: Mon Feb 13 20:43:08 2017

Remove SIMD.js from V8.

LOG=Y
BUG=v8:4124,v8:5948
R=bradnelson@chromium.org,bmeurer@chromium.org,jochen@chromium.org,hpayer@chromium.org,danno@chromium.org

Review-Url: https://codereview.chromium.org/2684313003
Cr-Original-Commit-Position: refs/heads/master@{#43162}
Committed: https://chromium.googlesource.com/v8/v8/+/d170c57ab996d00c4665a9d865bd5754a1806c6c
Review-Url: https://codereview.chromium.org/2684313003
Cr-Commit-Position: refs/heads/master@{#43169}

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Project Member

Comment 146 by bugdroid1@chromium.org, Feb 13 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/a386eb4f04b258a9e76cd0249146b4c856ee1cd6

commit a386eb4f04b258a9e76cd0249146b4c856ee1cd6
Author: franzih <franzih@chromium.org>
Date: Mon Feb 13 21:33:46 2017

Revert of Remove SIMD.js from V8. (patchset #7 id:120001 of https://codereview.chromium.org/2684313003/ )

Reason for revert:
Breaks Node integration build.

Original issue's description:
> Remove SIMD.js from V8.
>
> LOG=Y
> BUG=v8:4124,v8:5948
> R=bradnelson@chromium.org,bmeurer@chromium.org,jochen@chromium.org,hpayer@chromium.org,danno@chromium.org
>
> Review-Url: https://codereview.chromium.org/2684313003
> Cr-Original-Commit-Position: refs/heads/master@{#43162}
> Committed: https://chromium.googlesource.com/v8/v8/+/d170c57ab996d00c4665a9d865bd5754a1806c6c
> Review-Url: https://codereview.chromium.org/2684313003
> Cr-Commit-Position: refs/heads/master@{#43169}
> Committed: https://chromium.googlesource.com/v8/v8/+/a9b59a11f1bfe069afabe5567f919727456f1f12

TBR=bradnelson@chromium.org,bmeurer@chromium.org,jochen@chromium.org,hpayer@chromium.org,danno@chromium.org,bradnelson@google.com,machenbach@chromium.org,bbudge@chromium.org
# Skipping CQ checks because original CL landed less than 1 days ago.
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true
BUG=v8:4124,v8:5948

Review-Url: https://codereview.chromium.org/2695653005
Cr-Commit-Position: refs/heads/master@{#43170}

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Project Member

Comment 147 by bugdroid1@chromium.org, Feb 14 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/deabb19abc3328149ed76990cdd3a1d5e4e5b3ed

commit deabb19abc3328149ed76990cdd3a1d5e4e5b3ed
Author: bbudge <bbudge@chromium.org>
Date: Tue Feb 14 06:57:25 2017

Remove SIMD.js from V8.

LOG=Y
BUG=v8:4124,v8:5948
R=bradnelson@chromium.org,bmeurer@chromium.org,jochen@chromium.org,hpayer@chromium.org,danno@chromium.org

Review-Url: https://codereview.chromium.org/2684313003
Cr-Original-Original-Commit-Position: refs/heads/master@{#43162}
Committed: https://chromium.googlesource.com/v8/v8/+/d170c57ab996d00c4665a9d865bd5754a1806c6c
Review-Url: https://codereview.chromium.org/2684313003
Cr-Original-Commit-Position: refs/heads/master@{#43169}
Committed: https://chromium.googlesource.com/v8/v8/+/a9b59a11f1bfe069afabe5567f919727456f1f12
Review-Url: https://codereview.chromium.org/2684313003
Cr-Commit-Position: refs/heads/master@{#43176}

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Project Member

Comment 149 by bugdroid1@chromium.org, Feb 21 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/9fe0b4c7080daf0f52aaabf91ddaf0c6632cfbf8

commit 9fe0b4c7080daf0f52aaabf91ddaf0c6632cfbf8
Author: bbudge <bbudge@chromium.org>
Date: Tue Feb 21 16:45:30 2017

[V8] Implement SIMD Boolean vector types to allow mask registers.
- Adds new machine types SimdBool4/8/16 for the different boolean vector types.
- Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
- Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
  opcodes from the Boolean types. These are unlikely to be well supported natively,
  and can be synthesized using Select.
- Changes the signature of Relational opcodes to return boolean vectors.
- Changes the signature of Select opcodes to take boolean vectors.
- Updates the ARM implementation of Relational and Select opcodes.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2700813002
Cr-Commit-Position: refs/heads/master@{#43348}

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Project Member

Comment 150 by bugdroid1@chromium.org, Feb 25 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/d126e3fc5561a774cf5e4c70441ac585b2131e74

commit d126e3fc5561a774cf5e4c70441ac585b2131e74
Author: bbudge <bbudge@chromium.org>
Date: Sat Feb 25 15:41:27 2017

[V8] Rename SIMD Create methods and add initialization operators.

- Renames Create ops to Splat.
- Adds machine operators to initialize all SIMD machine types.
  Boolean vector types may need initialization, so provide zero
  operators.

LOG=N
BUG=v8:4124,695330

Review-Url: https://codereview.chromium.org/2719483002
Cr-Commit-Position: refs/heads/master@{#43430}

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[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/compiler/arm/instruction-scheduler-arm.cc
[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/compiler/arm/instruction-selector-arm.cc
[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/compiler/graph.h
[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/compiler/instruction-selector.cc
[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/compiler/machine-operator.cc
[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/compiler/machine-operator.h
[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/compiler/opcodes.h
[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/compiler/simd-scalar-lowering.cc
[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/compiler/wasm-compiler.cc
[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/compiler/wasm-compiler.h
[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/compiler/x64/code-generator-x64.cc
[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/compiler/x64/instruction-codes-x64.h
[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/compiler/x64/instruction-scheduler-x64.cc
[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/compiler/x64/instruction-selector-x64.cc
[modify] https://crrev.com/d126e3fc5561a774cf5e4c70441ac585b2131e74/src/wasm/function-body-decoder.cc

Status: WontFix (was: Assigned)
As we're now focusing solely on Wasm SIMD, let's start tracking that in a new issue:
https://bugs.chromium.org/p/v8/issues/detail?id=6020

Project Member

Comment 153 by bugdroid1@chromium.org, Feb 28 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/e6b9f07d4301e9041c1d8f6c1aa89c05aa5bc426

commit e6b9f07d4301e9041c1d8f6c1aa89c05aa5bc426
Author: aseemgarg <aseemgarg@chromium.org>
Date: Tue Feb 28 21:53:05 2017

[wasm]disable F32x4 and I32x4 cross ops test for arm as they break chromebook build

BUG=v8:4124
R=bradnelson@chromium.org,bbudge@chromium.org,gdeepti@chromium.org

Review-Url: https://codereview.chromium.org/2723823002
Cr-Commit-Position: refs/heads/master@{#43504}

[modify] https://crrev.com/e6b9f07d4301e9041c1d8f6c1aa89c05aa5bc426/test/cctest/wasm/test-run-wasm-simd.cc

Project Member

Comment 156 by bugdroid1@chromium.org, Mar 1 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/88c240bda5b0cf48e0eb08156a192a95fcf5e44b

commit 88c240bda5b0cf48e0eb08156a192a95fcf5e44b
Author: machenbach <machenbach@chromium.org>
Date: Wed Mar 01 12:39:48 2017

Revert of [wasm]implement simd lowering for f32x4->i32x4, i32x4 min/max and shift instructions (patchset #2 id:20001 of https://codereview.chromium.org/2718323003/ )

Reason for revert:
breaks nosse4:
https://build.chromium.org/p/client.v8/builders/V8%20Linux%20-%20debug/builds/13871

Original issue's description:
> [wasm]implement simd lowering for f32x4->i32x4, i32x4 min/max and shift instructions
>
> BUG=v8:4124
> R=bradnelson@chromium.org,bbudge@chromium.org,gdeepti@chromium.org,mtrofin@chromium.org,titzer@chromium.org
>
> Review-Url: https://codereview.chromium.org/2718323003
> Cr-Commit-Position: refs/heads/master@{#43510}
> Committed: https://chromium.googlesource.com/v8/v8/+/f75748cf4ca696fff268787068419604815f8090

TBR=bbudge@chromium.org,bradnelson@chromium.org,gdeepti@chromium.org,mtrofin@chromium.org,titzer@chromium.org,aseemgarg@chromium.org
# Skipping CQ checks because original CL landed less than 1 days ago.
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2723943003
Cr-Commit-Position: refs/heads/master@{#43512}

[modify] https://crrev.com/88c240bda5b0cf48e0eb08156a192a95fcf5e44b/src/compiler/simd-scalar-lowering.cc
[modify] https://crrev.com/88c240bda5b0cf48e0eb08156a192a95fcf5e44b/src/compiler/simd-scalar-lowering.h
[modify] https://crrev.com/88c240bda5b0cf48e0eb08156a192a95fcf5e44b/test/cctest/wasm/test-run-wasm-simd.cc

Project Member

Comment 157 by bugdroid1@chromium.org, Mar 22 2017

The following revision refers to this bug:
  https://chromium.googlesource.com/v8/v8.git/+/2747ab31ef64c7d2d0e5d726962bd9a382b0b0e8

commit 2747ab31ef64c7d2d0e5d726962bd9a382b0b0e8
Author: bbudge <bbudge@chromium.org>
Date: Wed Mar 22 19:18:47 2017

[WASM] Fix failing WASM SIMD tests.
- Skips test when expected value is very small or large.
- Renames methods to make more sense.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2764413003
Cr-Commit-Position: refs/heads/master@{#44045}

[modify] https://crrev.com/2747ab31ef64c7d2d0e5d726962bd9a382b0b0e8/test/cctest/wasm/test-run-wasm-simd.cc

Labels: Priority-2
Sad that V8 and Google Chrome does no more support SIMD. 
#159 - they will, but not using regular JavaScript. SIMD will probably be supported in Web Assembly. See issue 6020.
#160 - This is *very* disappointing for those of us that want to use SIMD in javascript though.  This also removes it from node.js and I had written a lot of code that used SIMD.  It doesn't make sense to remove the feature from one language and have the "replacement" be added to a different incompatible language.
For more context on this change, please see https://bugs.chromium.org/p/v8/issues/detail?id=6020&desc=2#c3

Please direct further questions to the new issue.
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