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Issue metadata

Status: Submitted
Owner: ----
Closed: Jan 31

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Issue 4614: Add Verilog/SystemVerilog syntax highlighting

Reported by, Sep 22 2016

Issue description

Affected Version: ?

What steps will reproduce the problem?
1. Upload Verilog/SystemVerilog source file.
2. View in PolyGerrit.

What is the expected output?

Syntax highlighting.

What do you see instead?

File looks like plain text.

Please provide any additional information below.

Comment 1 by, Sep 22 2016

Project Member
Labels: Priority-3
Status: Accepted (was: New)

Comment 2 by, Jul 27 2017

Project Member
Labels: Hotlist-SyntaxHighlighting

Comment 3 by, Jan 31

Project Member
Status: ChangeUnderReview (was: Accepted)

Comment 4 by, Jan 31

Project Member
Status: Submitted (was: ChangeUnderReview)

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