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Issue 913216 link

Starred by 1 user
Status: Assigned
Owner:
dlaurie@chromium.org
Cc:
adurbin@chromium.org
Components:
EstimatedDays: ----
NextAction: ----
OS: Chrome
Pri: 3
Type: Bug



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Cannonlake FSP is configuring GPIO pads it should not

Project Member Reported by dlaurie@google.com, Dec 8 
FSP-S is reconfiguring the display-related pads based on UPD configuration values, breaking the GPIO configuration done by BIOS.

FSP should not change GPIO pad configuration by default and these UPD settings should default to "skip" or "n/a" and only affect the GPIO pads if explicitly requested.


/** Offset 0x0228 - Enable or disable eDP device
  0=Disable, 1(Default)=Enable
  $EN_DIS
**/
  UINT8                       DdiPortEdp;

/** Offset 0x0229 - Enable or disable HPD of DDI port B
  0=Disable, 1(Default)=Enable
  $EN_DIS
**/
  UINT8                       DdiPortBHpd;

/** Offset 0x022A - Enable or disable HPD of DDI port C
  0=Disable, 1(Default)=Enable
  $EN_DIS
**/
  UINT8                       DdiPortCHpd;

/** Offset 0x022B - Enable or disable HPD of DDI port D
  0=Disable, 1(Default)=Enable
  $EN_DIS
**/
  UINT8                       DdiPortDHpd;

/** Offset 0x022C - Enable or disable HPD of DDI port F
  0=Disable, 1(Default)=Enable
  $EN_DIS
**/
  UINT8                       DdiPortFHpd;

/** Offset 0x022D - Enable or disable DDC of DDI port B
  0=Disable, 1(Default)=Enable
  $EN_DIS
**/
  UINT8                       DdiPortBDdc;

/** Offset 0x022E - Enable or disable DDC of DDI port C
  0=Disable, 1(Default)=Enable
  $EN_DIS
**/
  UINT8                       DdiPortCDdc;

/** Offset 0x022F - Enable or disable DDC of DDI port D
  0=Disable, 1(Default)=Enable
  $EN_DIS
**/
  UINT8                       DdiPortDDdc;

/** Offset 0x0230 - Enable or disable DDC of DDI port F
  0(Default)=Disable, 1=Enable
  $EN_DIS
**/
  UINT8                       DdiPortFDdc;
Project Member

Comment 1 by bugdroid1@chromium.org, Dec 11

Labels: merge-merged-chromeos-2016.05
The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/c8970786de0a18949245f68187b7a14b3a4e7eb7

commit c8970786de0a18949245f68187b7a14b3a4e7eb7
Author: Duncan Laurie <dlaurie@google.com>
Date: Tue Dec 11 05:47:36 2018

UPSTREAM: mb/google/sarien: Setup GPIOs again after FSP-S

Currently CoffeeLake FSP is incorrectly modifying GPIO pad configuration
if specific UPD variables are not set as it expects.

This affects the display-related SOC pads with the following UPD variables:

UINT8 DdiPortBHpd; // GPP_E13
UINT8 DdiPortCHpd; // GPP_E14
UINT8 DdiPortDHpd; // GPP_E15
UINT8 DdiPortFHpd; // GPP_E16
UINT8 DdiPortBDdc; // GPP_E18/GPP_E19
UINT8 DdiPortCDdc; // GPP_E20/GPP_E21
UINT8 DdiPortDDdc; // GPP_E22/GPP_E23
UINT8 DdiPortFDdc; // GPP_H16/GPP_H17

Until FSP is fixed to not touch the pad configuration this workaround
will reprogram the GPIO settings after FSP-S step so they are correct
when the OS attempts to use them.

This was found in CoffeLake FSP Gold release:
https://github.com/IntelFsp/FSP/tree/master/CoffeeLakeFspBinPkg

As well as the current top-of-tree for the FSP sources.

BUG=b:120686247,chromium:913216
TEST=verify correct GPIO configuration for GPP_E group in the kernel

Change-Id: I651ac9f7a0f45ea42da74dfa07f2071d411152b7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1a1f00cf413df295186a226150ca82d1f5d7ee23
Original-Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://review.coreboot.org/c/30113
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1370268
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>

[modify] https://crrev.com/c8970786de0a18949245f68187b7a14b3a4e7eb7/src/mainboard/google/sarien/ramstage.c

Comment 2 by benhenry@google.com, Jan 11

Status: Assigned (was: Untriaged)
This issue has an owner, a component and a priority, but is still listed as untriaged or unconfirmed. By definition, this bug is triaged. Changing status to "assigned". Please reach out to me if you disagree with how I've done this.
►

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