@Kirtika, as I mentioned in an email, I have taken this patches into our tree already.  We are probably going to release Core38 to you soon, so you can decide whether you want to apply all these patches in your trees or wait for our next release so you should get them already as part of our release.

Hi Luca,
I don't follow your comment - did you mean (a) you looked at these gerrit patches and applied them to your tree or (b) you already had made these fixes in your local tree before this bug? 
In either case, I think we want the PCI print related patches asap (I'll get Rajat to review those). The rest can wait. 
For schedule info:
R69 branch will be cut July 19th, it goes to stable Sept 11th.
R70 branch cut is August 30th, it goes to stable Oct 23rd. 

If I get Core38 by July 4th or so, I can get it by branch cut on July 19th.

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/1d4cd2dd6788f0d196f07296885a67cef86c6d75

commit 1d4cd2dd6788f0d196f07296885a67cef86c6d75
Author: Rajat Jain <rajatja@google.com>
Date: Tue Jun 19 04:14:12 2018

BACKPORT: PCI/ASPM: Add L1 substate capability structure register definitions

Add L1 substate capability structure register definitions for use in
subsequent patches.  See the PCIe r3.1 spec, sec 7.33.

[bhelgaas: add PCIe spec reference]
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
(cherry picked from commit 0fc1223f0e77a748f7040562faaa7027f7db71ca)

rajatja: The backport is due to the following definitions that are not
part of the upstream commit but picked up here for consistency:
+#define PCI_EXT_CAP_ID_DPC     0x1D    /* Downstream Port Containment */
+#define PCI_EXT_CAP_ID_PTM     0x1F    /* Precision Time Measurement */

BUG=b:35648315, chromium:853562
TEST=trybot on link, boot on falco_li
Change-Id: I03cecce59877cc1e2149bac4d009adb7365e8c58
Reviewed-on: https://chromium-review.googlesource.com/1050991
Commit-Ready: Rajat Jain <rajatja@chromium.org>
Tested-by: Rajat Jain <rajatja@chromium.org>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Reviewed-by: Kirtika Ruchandani <kirtika@chromium.org>
(cherry picked from commit ac35938d092032c9193800fec2997ad932288feb)
Reviewed-on: https://chromium-review.googlesource.com/1103496
Commit-Ready: Kirtika Ruchandani <kirtika@chromium.org>
Tested-by: Kirtika Ruchandani <kirtika@chromium.org>
Reviewed-by: Rajat Jain <rajatja@chromium.org>

[modify] https://crrev.com/1d4cd2dd6788f0d196f07296885a67cef86c6d75/include/uapi/linux/pci_regs.h

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/5bbb46d6c72bb52f3ac1c99c0808d7d53168456c

commit 5bbb46d6c72bb52f3ac1c99c0808d7d53168456c
Author: Rajat Jain <rajatja@google.com>
Date: Tue Jun 19 04:14:14 2018

CHROMIUM: iwl7000: Print the L1 substate status along with L1/LTR

Dump the L1 substate status also along with L1 and LTR status.

CQ-DEPEND=CL:1103496
BUG=b:35648315, chromium:853562
TEST=build and boot on falco_li, verify messages

Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Kirtika Ruchandani <kirtika@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1050992
Commit-Ready: Rajat Jain <rajatja@chromium.org>
Tested-by: Rajat Jain <rajatja@chromium.org>
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Rajat Jain <rajatja@chromium.org>
Change-Id: Ia782750cf7e54af69bb22a66c45cf33c63a07701
Reviewed-on: https://chromium-review.googlesource.com/1103847
Commit-Ready: Kirtika Ruchandani <kirtika@chromium.org>
Tested-by: Kirtika Ruchandani <kirtika@chromium.org>
Reviewed-by: Kirtika Ruchandani <kirtika@chromium.org>

[modify] https://crrev.com/5bbb46d6c72bb52f3ac1c99c0808d7d53168456c/drivers/net/wireless/iwl7000/iwlwifi/pcie/trans.c

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/6b580801cdb6b61d4b2513f8d06e880d4a7c16eb

commit 6b580801cdb6b61d4b2513f8d06e880d4a7c16eb
Author: Rajat Jain <rajatja@google.com>
Date: Wed Jun 20 02:11:03 2018

BACKPORT: PCI/ASPM: Add L1 substate capability structure register definitions

Add L1 substate capability structure register definitions for use in
subsequent patches.  See the PCIe r3.1 spec, sec 7.33.

[bhelgaas: add PCIe spec reference]
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
(cherry picked from commit 0fc1223f0e77a748f7040562faaa7027f7db71ca)

rajatja: The backport is due to the following definitions that are not
part of the upstream commit but picked up here for consistency:
+#define PCI_EXT_CAP_ID_DPC     0x1D    /* Downstream Port Containment */
+#define PCI_EXT_CAP_ID_PTM     0x1F    /* Precision Time Measurement */

BUG=b:35648315, chromium:853562
TEST=trybot on cyan
Change-Id: I03cecce59877cc1e2149bac4d009adb7365e8c58
Reviewed-on: https://chromium-review.googlesource.com/1050991
Commit-Ready: Rajat Jain <rajatja@chromium.org>
Tested-by: Rajat Jain <rajatja@chromium.org>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Reviewed-by: Kirtika Ruchandani <kirtika@chromium.org>
(cherry picked from commit ac35938d092032c9193800fec2997ad932288feb)
Reviewed-on: https://chromium-review.googlesource.com/1103493
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Kirtika Ruchandani <kirtika@chromium.org>

[modify] https://crrev.com/6b580801cdb6b61d4b2513f8d06e880d4a7c16eb/include/uapi/linux/pci_regs.h

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/d9bce4bb2155859248665e16b5fee2085729d880

commit d9bce4bb2155859248665e16b5fee2085729d880
Author: Rajat Jain <rajatja@google.com>
Date: Wed Jun 20 02:11:04 2018

CHROMIUM: iwl7000: Print the L1 substate status along with L1/LTR

Dump the L1 substate status also along with L1 and LTR status.

BUG=b:35648315, chromium:853562
TEST=verify the messages on boot

Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Kirtika Ruchandani <kirtika@google.com>
Change-Id: Ia782750cf7e54af69bb22a66c45cf33c63a07701
Reviewed-on: https://chromium-review.googlesource.com/1050992
Commit-Ready: Rajat Jain <rajatja@chromium.org>
Tested-by: Rajat Jain <rajatja@chromium.org>
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Rajat Jain <rajatja@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1103850
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Kirtika Ruchandani <kirtika@chromium.org>
Reviewed-by: Kirtika Ruchandani <kirtika@chromium.org>

[modify] https://crrev.com/d9bce4bb2155859248665e16b5fee2085729d880/drivers/net/wireless-3.8/iwl7000/iwlwifi/pcie/trans.c

Kirtika,

I meant (b).  Two weeks ago, I merged your trees into our internal clones of chromeos trees and, in order not to lose the changes you had made, I took all the relevant patches to our "stack-dev" tree (from which we generate iwl7000).  If I hadn't done that, our iwl7000 generation would have automatically reverted those changes.  While doing this, I aligned all chromeos trees (3.8, 3.14, 3.18, 4.4 and 4.14) because our generation scripts always keep the resulting sources identical for all 5 versions.

In any case, it's your choice, you can take all the patches to all your trees now, if you want.  When we release Core38, the changes will be there too.

I'll ask Dor what is the release schedule for Core38 and see if we will be ready on time for R69.

Luca, thanks for the explanation. 
Thinking some more about it, unless others have objections, later would be better for Core38. I am certain I have err-ed with Core31 and Core35, merging them in a rush and not giving Intel the testing feedback that I did until Core28 (partly due to the cfg churn - Core31 introduced it and Core35 removed it). 
It would be nice to delay Core38 to R70 (branch is cut Aug 30) so that I have some time to look through current crashes and feedbacks and file bugs for Intel. 

Makes sense.  It's better not to rush things and merge just before the branch out.  I'll discuss this with Dor so we are all aligned.