Cannot flash EC with cr50 on grunt |
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Issue description$ ./util/flash_ec --board grunt --port 7777 INFO: Using servo_v4. INFO: Using ec image : /build/grunt/firmware/ec.bin INFO: Flashing chip npcx_spi. Problem with ['cold_reset:on'] :: No control named "cold_reset" $ dut-control -p 7777 cold_reset Problem with ['cold_reset'] :: No control named "cold_reset" I am following instructions from 'How to use CCD on Cr50' Assigning to Mary for advice
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Apr 4 2018
When you start up servo does it print SystemConfig - INFO - Loading XML config (/usr/lib64/python2.7/site-packages/servo/data/ccd_cr50.xml, None, 0)
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Apr 4 2018
Have you run through ccd open? And is cr50 open when you're trying to use flash_ec?
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Apr 6 2018
I just tried this using a SuzyQ cable and it's failing.
cr50> version
Chip: g cr50 B2-C
Board: 0
RO_A: * 0.0.10/29d77172
RO_B: 0.0.10/c2a3f8f9
RW_A: 0.3.4/cr50_v1.9308_87_mp.30-a9768e0
RW_B: * 0.4.4/cr50_v1.9308_B.334-78f874b
BID A: 00000000:00000000:00000000 Yes
BID B: 46464646:00000000:00000010 Yes
Build: 0.4.4/cr50_v1.9308_B.334-78f874b
tpm2:v0.0.291-af944a7
cryptoc:v0.0.8-6283eee
2018-02-20 23:24:38 @build21-m2.golo.chromium.org
cr50> ccd
State: Opened
Password: none
Flags: 0x000001
Capabilities: 0000000000000000
UartGscRxAPTx Y 0=Default (Always)
UartGscTxAPRx Y 0=Default (Always)
UartGscRxECTx Y 0=Default (Always)
UartGscTxECRx Y 0=Default (IfOpened)
FlashAP Y 0=Default (IfOpened)
FlashEC Y 0=Default (IfOpened)
OverrideWP Y 0=Default (IfOpened)
RebootECAP Y 0=Default (IfOpened)
GscFullConsole Y 0=Default (IfOpened)
UnlockNoReboot Y 0=Default (Always)
UnlockNoShortPP Y 0=Default (Always)
OpenNoTPMWipe Y 0=Default (IfOpened)
OpenNoLongPP Y 0=Default (IfOpened)
BatteryBypassPP Y 0=Default (Always)
UpdateNoTPMWipe Y 0=Default (Always)
I2C Y 0=Default (IfOpened)
FlashRead Y 0=Default (Always)
cr50> wp
Flash WP: forced disabled
at boot: follow_batt_pres
(chroot)$ /usr/bin/flash_ec --board grunt --verbose
dut-control --port=9999 servo_type
INFO: Using ccd_cr50.
INFO: Using ec image : /build/grunt/firmware/ec.bin
INFO: Flashing chip npcx_spi.
dut-control --port=9999 cold_reset:on
dut-control --port=9999 fw_up:on
dut-control --port=9999 cold_reset:off
Running flashrom:
sudo /usr/sbin/flashrom -p raiden_debug_spi:target=EC,serial=0581003A-91A0D343 --get-size
Running flashrom:
/usr/sbin/flashrom -p raiden_debug_spi:target=EC,serial=0581003A-91A0D343 -i EC_RW -i WP_RO -l /tmp/flash_spi_layout_119773 --ignore-fmap --fast-verify -w /tmp/flash_spi_119773
flashrom v0.9.9 : db13358 : Mar 27 2018 21:58:16 UTC on Linux 4.9.0-6-amd64 (x86_64)
flashrom v0.9.9 : db13358 : Mar 27 2018 21:58:16 UTC on Linux 4.9.0-6-amd64 (x86_64)
Calibrating delay loop... OK.
Raiden: Serial number 0581003A-91A0D343 matched device bus=0x01,address=0x2e | Cr50
Read is not working on this chip. Aborting.
FAILED
dut-control --port=9999 cold_reset:on
dut-control --port=9999 cold_reset:off
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Apr 6 2018
sudo /usr/sbin/flashrom -p raiden_debug_spi:target=EC,serial=0581003A-91A0D343 --get-size is reporting size 0
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Apr 6 2018
,
Apr 6 2018
You need to assert ecrst before you try flashing. If you're running through servo, use dut-control cold_reset:on If you're running without servo, use 'ecrst on' in the cr50 console
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Apr 6 2018
Can you also upload the cr50 console output from when flash_ec was running?
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Apr 6 2018
This is using the SuzyQ cable. Flashing the EC via a ServoV2 works fine. > ecrst on <-- I did this one manually EC_RST_L is asserted > > ecrst on <-- This happened when I ran flash_ec. EC_RST_L is asserted > > gpioset EC_FLASH_SELECT 1 > > ecrst off EC_RST_L is deasserted > [70505.023977 enable_spi_pinmux: EC] [70505.038614 usb_spi_board_disable] [70505.628080 enable_spi_pinmux: EC] [70505.640962 usb_spi_board_disable] > > ecrst EC_RST_L is deasserted > > ecrst on EC_RST_L is asserted > > ecrst off EC_RST_L is deasserted > [70506.939443 AC: -F] [70507.069765 AP UART on] [70507.072282 CCD state: UARTAP+TX UARTEC+TX I2C SPI] [70507.137594 deferred_tpm_rst_isr] [70507.139287 AP on] [70507.140489 tpm_reset_request(0, 0)] [70507.142042 tpm_reset_now(0)] [70507.146455 tpm_init] tpm_manufactured: manufactured The flash_ec output is the same as #4
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Apr 6 2018
Hmm. Everything looks fine on the cr50 console. You don't still have servo connected right?
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Apr 6 2018
Nope. Servo is not connected to either host or DUT. DUT only has suzyq cable.
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Apr 6 2018
Can you try running things manually. Stop servod unplug suzyq wait 5 seconds plug it back in run ecrst on sudo /usr/sbin/flashrom -p raiden_debug_spi:target=EC,serial=0581003A-91A0D343 -r image.bin run ecrst off
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Apr 6 2018
> ecrst on EC_RST_L is asserted $ sudo /usr/sbin/flashrom -p raiden_debug_spi:target=EC,serial=0581003A-91A0D343 -r /build/grunt/firmware/ec.bin flashrom v0.9.9 : db13358 : Mar 27 2018 21:58:16 UTC on Linux 4.9.0-6-amd64 (x86_64) flashrom v0.9.9 : db13358 : Mar 27 2018 21:58:16 UTC on Linux 4.9.0-6-amd64 (x86_64) Calibrating delay loop... OK. Raiden: Serial number 0581003A-91A0D343 matched device bus=0x01,address=0x32 | Cr50 Read is not working on this chip. Aborting. FAILED > [207.387172 enable_spi_pinmux: EC] [207.399406 usb_spi_board_disable] [224.208179 enable_spi_pinmux: EC] [224.220256 usb_spi_board_disable]
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Apr 6 2018
Does Grunt use uart bitbang to program the EC?
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Apr 9 2018
Does flashing the AP work? Do you know if anyone has successfully flashed the EC from cr50 on grunt?
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Apr 10 2018
I thought that Grunt uses JTAG to program the EC. How can we tell? I am able to flash the AP through servo v4, although I did not try Suzy-Q. It's on the EC with servo_v4 that I have trouble with, and from what Raul says above, Suzy-Q does not work either.
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Apr 10 2018
I was able to flash the AP using the Suzy-Q cable. I'm wondering if we have a problem in the schematic. Not sure if grunt is using UART bit bang or JTAG. I'll dig in.
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Apr 12 2018
Created this bug: https://b.corp.google.com/issues/77927814 in buganizer under Cr50 hotlist to track this issue. Lets close this crbug and instead use buganizer for ease of tracking internal project progress.
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Aug 3
This bug has an owner, thus, it's been triaged. Changing status to "assigned".
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Aug 3
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Comment 1 by sjg@chromium.org
, Mar 30 2018