Luis, can you talk with ARM regarding this in the next meeting?

Btw, I do have a patch to address it.

#2: Great, thanks! Please let me know when it is uploaded for upstream LLVM review, then we can use it to convince kernel folks that a LLVM fix is underway.

mka@, A counter example for GCC was just posted on the llvm bug
https://bugs.llvm.org/show_bug.cgi?id=36862

int function(void)
{
    asm("mov r0,r0\n");
    return 0;
}

Error: operand 1 should be an integer register -- 'mov r0,r0'

Maybe this is enough to counter that GCC supports "r" registers in all cases?

Hmm, gcc 6.3 and 7.2 actually supports the above example.

From https://bugs.llvm.org/show_bug.cgi?id=36862 :

"From the kernel patch it looks like that this is only being used in restricted cases, for example register constraints. Do you have a list of what can and can't be given as "r"?"

For this bug it should indeed be sufficient to supports rN for register constraints, not sure if rN could be used in other contexts in the future though.

Probably best to check with ARM folks, if you want I can loop you in to the kernel thread where 3 ARM employees participated. Or you can reach out privately: Robin Murphy <robin.murphy@arm.com>, Dave Martin <Dave.Martin@arm.com>, Marc Zyngier <marc.zyngier@arm.com>

Sent the patch at https://reviews.llvm.org/D44815

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/ef4b52b72f55d62765eccd091446f754221cb264

commit ef4b52b72f55d62765eccd091446f754221cb264
Author: Manoj Gupta <manojgupta@google.com>
Date: Tue Apr 03 08:29:15 2018

llvm: Cherry-pick clang for parsing rN registers in AArch64.

CL summary:
Author:     Manoj Gupta <manojgupta@google.com>

    [AArch64]: Add support for parsing rN registers.

    Summary:
    Allow rN registers to be simply parsed as correspoing xN registers.
    The "register ... asm("rN")" is an command to the
    compiler's register allocator, not an operand to any individual assembly
    instruction. GCC documents this syntax as "...the name of the register
    that should be used."

    This is needed to support the changes in Linux kernel (see
    https://lkml.org/lkml/2018/3/1/268 )

BUG= chromium:824526 
TEST=sudo emerge llvm works.

Change-Id: I159b98e51f38e782daa6941650b292ba40125450
Reviewed-on: https://chromium-review.googlesource.com/990583
Commit-Ready: Manoj Gupta <manojgupta@chromium.org>
Tested-by: Manoj Gupta <manojgupta@chromium.org>
Reviewed-by: Ting-Yuan Huang <laszio@chromium.org>

[rename] https://crrev.com/ef4b52b72f55d62765eccd091446f754221cb264/sys-devel/llvm/llvm-7.0_pre326829_p20180318-r6.ebuild
[add] https://crrev.com/ef4b52b72f55d62765eccd091446f754221cb264/sys-devel/llvm/files/cherry/8c8aea3ce916068052d4e4029f6878d8d7dd53da.patch

Matthias, I have cherry-picked the upstream  patch to Chrome OS clang. Is it possible for you to test the upstream ARM64 kernel with it?

Running "sudo emerge llvm" should pull in the new llvm (version llvm-7.0_pre326829_p20180318-r6).

upstream ToT and CrOS v4.14 build with the latest LLVM. Thanks!

Thanks Manoj for implementing this! :D