Kabylake uses the same PMU as Skylake. The relevant patch just adds the Kabylake model numbers.

I cherry picked a few more commits that improve PEBS support, which were touching nearby lines.

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/47f40e2994b267887bd87a5d3b64665a941b780e

commit 47f40e2994b267887bd87a5d3b64665a941b780e
Author: Andi Kleen <ak@linux.intel.com>
Date: Mon Mar 26 17:48:42 2018

BACKPORT: perf/x86: Add model numbers for Kabylake CPUs

Everything the same as Skylake, just new model numbers.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1461977748-17616-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit cba1b3798e2c4c094f2079a0d4c1ba4ec2c5a9ac)
Signed-off-by: Gabriel Marin <gmx@chromium.org>

Conflicts:
	arch/x86/events/intel/core.c
	Added changes to arch/x86/kernel/cpu/perf_event_intel.c, which is the
	old location of Intel perf events before code reorganization upstream.

BUG= chromium:820661 ,b:74020465
TEST=Build and run. Verified that collection of LBR traces, and iTLB and dTLB
     misses on Kabylake works.

Change-Id: I5b5751c945ddef1f7da43012b41c4d279234066f
Reviewed-on: https://chromium-review.googlesource.com/957973
Commit-Ready: Gabriel Marin <gmx@chromium.org>
Tested-by: Gabriel Marin <gmx@chromium.org>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
(cherry picked from commit 16dad81c709341c9d4cb515931ece299fde318fd)
Reviewed-on: https://chromium-review.googlesource.com/980920
Trybot-Ready: Gabriel Marin <gmx@chromium.org>
Commit-Queue: Gabriel Marin <gmx@chromium.org>

[modify] https://crrev.com/47f40e2994b267887bd87a5d3b64665a941b780e/arch/x86/kernel/cpu/perf_event_intel.c