It looks bad on the surface because the lack of GPIOs on one board seems to be dictating our system design for all boards. But, I could see us implementing this in the PDCMD task even if we didn't have GPIO constraints, the code is cleaner than using a deferred task.

Apart from the hardware limitation being a terrible idea,
normally on a theoretical point of view, shared interrupt lines need to be level-triggered rather than edge-triggered to work properly (and in the linux kernel world we would service them from a 'threaded irq handler' effectively disabling the interrupt request until a lower priority kernel thread has done the I2C accesses to read the statuses for each user)
As noted by Aseda in the CL, level-triggered currently doesn't work (likely because you have to disable irq until the I2C status read+clear happens)
For TCPC, the Alert# line is designed to work with a level-sensitive host no issue there.

Overall, there are 2 parts in the design issue:
a. if we keep it edge-triggered, it seems we will still need to do Aseda trick (ie re-call the ISR if the line is still asserted), and this seems somewhat difficult to fully avoid small race conditions around this.
b. we need to decide where to check the status of both (shared) user of the interrupt line.
  Shawnn proposal looks the more robust.