npcx: i2c: 1 MHz I2C not supported at 15 MHz core |
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Issue descriptionTo configure 1 MHz speed when the APB clock is 15 MHz (and core clock is also 15 MHz), the firmware currently sets the SCLHT register to 4. However, we found out that writing 4 to this register (and to SCLLT register) is illegal and results in unexpected results. So there is a need to write 5 in that case. However, this means that the actual I2C frequency will be 750 KHz. To get a higher I2C clock frequency, there is a need to run with a higher APB clock (and a higher core clock). For example, with APB set to 20 MHz, the I2C clock frequency is 833 KHz. So far, the only launched board affected by this is Kevin. Fixed by https://chromium-review.googlesource.com/484202
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May 1 2017
A more detailed analysis of setting SCHLT=4 is that it increases some of the bus times so effective bus frequency is slower than expected, but it doesn't cause any I2C spec violations. So while we should fix this on future systems, it's not critical to push this fix to already-shipped systems.
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May 10 2017
The following revision refers to this bug: https://chromium.googlesource.com/chromiumos/platform/ec/+/60d678623b0331d35a3dc57ed3eddc087526cbef commit 60d678623b0331d35a3dc57ed3eddc087526cbef Author: CHLin <CHLIN56@nuvoton.com> Date: Wed May 10 01:09:02 2017 npcx: i2c: Fix i2c freq setting when APB clock is 15 MHz To configure 1 MHz speed when the APB clock is 15 MHz, the firmware currently sets the SCLHT register to 4. However, we found out that writing 4 to this register (and to SCLLT register) is illegal and results in unexpected results. So there is a need to write 5 in that case. However, this means that the actual i2c frequency will be 750 KHz. To get a higher i2c clock frequency, there is a need to run with a higher APB clock (and a higher core clock). For example, with APB set to 20 MHz, the i2c clock frequency is 833 KHz. In this CL, the i2c freq setting for APB clock=20 MHz is also added which may be used for NPCX7 in the future. BRANCH=none BUG= chromium:714314 TEST=No build error for make buildall(except gru). Use scope to capture SCL signal on npcx5 EVB and make sure its freqency is about 750 KHz. Change-Id: I9025344e6df4b584b203c8c59bb9875250d9fe4f Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/484202 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/499830 Commit-Queue: Caesar Wang <wxt@rock-chips.com> Tested-by: Caesar Wang <wxt@rock-chips.com> [modify] https://crrev.com/60d678623b0331d35a3dc57ed3eddc087526cbef/chip/npcx/i2c.c
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Aug 1 2017
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Jan 22 2018
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Comment 1 by bugdroid1@chromium.org
, Apr 25 2017