Issue 675043 link

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Issue metadata

Status:	Archived
Owner:	reinauer@chromium.org
Closed:	Jan 2017
Cc:	jwer...@chromium.org █ waihong@chromium.org adurbin@chromium.org
Components:	OS>Firmware>BIOS
EstimatedDays:	----
NextAction:	----
OS:	Chrome
Pri:	2
Type:	Bug
merge-merged-chromeos-2016.05 VerifyIn-58 VerifyIn-59 VerifyIn-60 VerifyIn-61

veyron_jerry coreboot fails with i2c assertion

Project Member Reported by rspangler@chromium.org, Dec 16 2016

Issue description

coreboot-coreboot-unknown.9999.1bad668 Fri Dec 16 18:26:15 UTC 2016 bootblock starting...
Exception handlers installed.
Configuring PLL at ff760030 with NF = 99, NR = 2 and NO = 2 (VCO = 1188000KHz, output = 594000KHz)
Configuring PLL at ff760020 with NF = 32, NR = 1 and NO = 2 (VCO = 768000KHz, output = 384000KHz)
Translation table is @ ff700000
Mapping address range [0x00000000:0x00000000) as uncached
Creating new subtable @ff716c00 for [0xff700000:0xff800000)
Mapping address range [0xff700000:0xff718000) as writethrough
I2C bus 0: 386718Hz (divh = 9, divl = 13)
ASSERTION ERROR: file 'src/soc/rockchip/common/i2c.c', line 289

If I comment out that assertion, it boots all the way to depthcharge then fails with a timeout during EC software sync.

That assertion seems to have been added recently:

9b820560 src/soc/rockchip/common/i2c.c (Julius Werner  2016-11-01 15:24:54 -0700 289)   assert((divh < 65536) && (divl < 65536) && hz - i2c_clk < 10*KHz);

Comment 1 by rspangler@chromium.org, Dec 16 2016

Cc: waihong@chromium.org

Note that this is compiled from ToT.  The version from the branch likely works.

Project Member

Comment 2 by bugdroid1@chromium.org, Dec 17 2016

Labels: merge-merged-chromeos-2016.05

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/50ff17107dc6bec50697da987f07e5b355d02719

commit 50ff17107dc6bec50697da987f07e5b355d02719
Author: Julius Werner <jwerner@chromium.org>
Date: Sat Dec 17 00:03:57 2016

rockchip/common: Loosen I2C frequency target requirements

I've recently added an assertion to ensure that the effective I2C
frequency on Rockchip SoCs is not too far off the 400KHz target due to
divisor rounding errors. A 10KHz margin worked fine for RK3399, but it
turns out that RK3288 actually only ever hit 387KHz since its I2C clocks
are based off the already pretty low 75MHz PCLKs. While we could
probably change the PCLKs to make this closer, that seems like a too
intrusive change for something that has already worked just fine for
years, so just loosen the restriction a little more instead.

BRANCH=None
BUG= chromium:675043 
TEST=None

Change-Id: I7e96a1a75b38f8ad3971dd33046699cceb17b80d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421095
Reviewed-by: Randall Spangler <rspangler@chromium.org>

[modify] https://crrev.com/50ff17107dc6bec50697da987f07e5b355d02719/src/soc/rockchip/common/i2c.c