Hi Tom,
I found that on nyan_big, WaitVideoOutputStable often fails.
This affects test with audio/video dumping.
I added more logs and tried to see what caused the failure.
It seems that chameleond thinks receiver is in dual mode (by comparing the PCLK with _PIXEL_MODE_PCLK_THRESHOLD_HIGH (130MHz)
However, what got from FPGA is that receiver only dumps to one VideoDumper.
So, instead of [(960, 1200), (960, 1200)], it gets [(0, 0), (1920, 1200)]
I am not sure if this means receiver is working in single pixel mode.
In field manager, it computes the resolution as (0 + 1920, 0).
https://cs.corp.google.com/chromeos_public/src/platform/chameleon/chameleond/utils/field_manager.py?type=cs&q=ComputeResolution+package:%5Echromeos_public$&l=68
So, we get different resolution forever.
I have tried increasing the timeout but that does not help.

2016-06-30 22:33:47,575 INFO PCLK = 134.652439024                                                                                             
2016-06-30 22:33:47,576 INFO _is_dual_pixel_mode = True                                                                                       
2016-06-30 22:33:47,576 INFO dual_pixel_mode = True                                                                                           
2016-06-30 22:33:47,577 INFO Do_FSM: pixel_mode_changed: False                                                                                
2016-06-30 22:33:47,579 INFO resolutions in field manager in dual: [(0L, 0L), (1920L, 1200L)]                                                 
2016-06-30 22:33:47,579 WARNING Different resolutions between paths: 0x0 != 1920x1200                                                         
2016-06-30 22:33:47,586 INFO fpga resolution: 1920x0                                                                                          
2016-06-30 22:33:47,587 INFO rx resolution: 1920x1200                                                                                         
2016-06-30 22:33:47,587 INFO diff resolution: fpga:1920x0 != rx:1920x1200 

I am not sure what is the mechanism to detect whether receiver is in dual frame mode.
The comment in the code is confusing.

  # The firmware for the 6803 reference board sets the rx in dual pixel mode
  # when the pixel clock is greater than 160. Here, we use 130 instead of 160
  # as the FPGA works more reliably when the pixel clock is under this value.
  # Two thresholds defining a hysteresis zone to avoid rapid mode changes due
  # to pixel clock noise.

In the above instance, receiver seems to be working in single pixel mode at PCLK = 134.652MHz

In another instance, receiver works in dual mode at 131.446MHz

2015-09-29 01:33:51,287 INFO PCLK = 131.446428571                                               
2015-09-29 01:33:51,287 INFO _is_dual_pixel_mode = True                                           
2015-09-29 01:33:51,288 INFO Do not change mode for hysteresis. Return                     
2015-09-29 01:33:51,288 INFO Do_FSM: pixel_mode_changed: False                             
2015-09-29 01:33:51,290 INFO resolutions in field manager in dual: [(960L, 1200L), (960L, 1200L)]
2015-09-29 01:33:51,298 INFO fpga resolution: 1920x1200
2015-09-29 01:33:51,298 INFO rx resolution: 1920x1200                
2015-09-29 01:33:51,299 INFO same resolution: 1920x1200

I am wondering if there is a better way to detect whether device is dual mode or single mode.

There was an old issue https://bugs.chromium.org/p/chromium/issues/detail?id=453416#c73
changing the threshold value of mode from [115, 125] to [126, 130]. It seems that using PCLK to detect mode is not a reliable approach.

Could you please take a look if we can detect mode reliably?
Thanks a lot!