https://chromium-review.googlesource.com/#/q/topic:airmont_tsc

Before patchset: evaluated two power cycles

localhost ~ # dmesg | grep -i tsc
[    0.000000] Initial TSC value: 13948786920
[    0.000000] tsc: Fast TSC calibration using PIT
[    0.000000] tsc: Detected 1600.011 MHz processor
[    0.041589] TSC deadline timer enabled
[    1.260668] tsc: Refined TSC clocksource calibration: 1599.948 MHz
[    2.261262] Switched to clocksource tsc

[    0.000000] Initial TSC value: 13946729800
[    0.000000] tsc: Fast TSC calibration using PIT
[    0.000000] tsc: Detected 1600.013 MHz processor
[    0.041474] TSC deadline timer enabled
[    1.259560] tsc: Refined TSC clocksource calibration: 1599.948 MHz
[    2.262048] Switched to clocksource tsc


After patchset: evaluated two power cycles
[    0.000000] Initial TSC value: 13947330860
[    0.000000] TSC runs at 1600000 KHz
[    0.000000] tsc: Detected 1600.000 MHz processor
[    0.041420] TSC deadline timer enabled
[    1.260483] tsc: Refined TSC clocksource calibration: 1599.938 MHz
[    2.264334] Switched to clocksource tsc

[    0.000000] Initial TSC value: 13947017180
[    0.000000] TSC runs at 1600000 KHz
[    0.000000] tsc: Detected 1600.000 MHz processor
[    0.041522] TSC deadline timer enabled
[    1.260599] tsc: Refined TSC clocksource calibration: 1599.948 MHz
[    2.264456] Switched to clocksource tsc

made another one considering Skylake as well:
https://chromium-review.googlesource.com/#/q/topic:tsc_calibration

Rebased and refined topic branch as most of the patches landed on upstream recently; besides, evaluated on BYT/BSW/BDW/SKL:

BYT (rambi):
[    0.000000] Initial TSC value: 11452294906
[    0.000000] tsc: Detected 2165.800 MHz processor
[    0.039861] TSC deadline timer enabled
[    0.278761] ACPI: Sleep Button [TSCR]
[    1.266508] tsc: Refined TSC clocksource calibration: 2166.666 MHz 
[    2.267010] Switched to clocksource tsc 

BSW (celes):
[    0.000000] Initial TSC value: 9129820500
[    0.000000] tsc: Detected 1600.000 MHz processor
[    0.041122] TSC deadline timer enabled
[    1.255185] tsc: Refined TSC clocksource calibration: 1599.948 MHz 
[    2.255618] Switched to clocksource tsc 

BDW (lulu):
[    0.000000] Initial TSC value: 7714076868
[    0.000000] tsc: Fast TSC calibration using PIT 
[    0.000000] tsc: Detected 1995.438 MHz processor
[    0.028208] TSC deadline timer enabled
[    1.515617] tsc: Refined TSC clocksource calibration: 1995.383 MHz 
[    2.518491] Switched to clocksource tsc 

SKL (chell):
[    0.000000] Initial TSC value: 8733129006
[    0.000000] tsc: Detected 900.000 MHz processor
[    0.034757] TSC deadline timer enabled
[    1.223428] tsc: Refined TSC clocksource calibration: 911.998 MHz 
[    2.223131] Switched to clocksource tsc

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/7ed1bc326eb51ba2633fa410fd25bf6dd853570f

commit 7ed1bc326eb51ba2633fa410fd25bf6dd853570f
Author: Adrian Hunter <adrian.hunter@intel.com>
Date: Fri Aug 21 09:05:18 2015

UPSTREAM: perf/x86: Improve accuracy of perf/sched clock

When TSC is stable perf/sched clock is based on it.
However the conversion from cycles to nanoseconds
is not as accurate as it could be.  Because
CYC2NS_SCALE_FACTOR is 10, the accuracy is +/- 1/2048

The change is to calculate the maximum shift that
results in a multiplier that is still a 32-bit number.
For example all frequencies over 1 GHz will have
a shift of 32, making the accuracy of the conversion
+/- 1/(2^33).  That is achieved by using the
'clocks_calc_mult_shift()' function.

BUG=chrome-os-partner:50692, chromium:624029
TEST=dmesg | grep -i tsc # examine TSC calibration flow

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/1440147918-22250-1-git-send-email-adrian.hunter@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit b20112edeadf0b8a1416de061caa4beb11539902)
Signed-off-by: Harry Pan <harry.pan@intel.com>

Change-Id: I235d3a81b590d81ac6bc8dbdf3f2bcbcdd5ee41e
Reviewed-on: https://chromium-review.googlesource.com/356960
Commit-Ready: Harry Pan <harry.pan@intel.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

[modify] https://crrev.com/7ed1bc326eb51ba2633fa410fd25bf6dd853570f/arch/x86/kernel/tsc.c

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/c7dca2d0386188fdb76e83c45ebaaef3783796a8

commit c7dca2d0386188fdb76e83c45ebaaef3783796a8
Author: Borislav Petkov <bp@suse.de>
Date: Tue Apr 05 06:29:53 2016

BACKPORT: x86/tsc: Save an indentation level in recalibrate_cpu_khz()

... by flipping the check.

BUG=chrome-os-partner:50692, chromium:624029
TEST=dmesg | grep -i tsc # examine TSC calibration flow

Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1459837795-2588-5-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit eff4677e9fb9b680d1d5f6ba079116548d072b7e)
Signed-off-by: Harry Pan <harry.pan@intel.com>

Conflicts:
	arch/x86/kernel/tsc.c
(Skip dependency of 59e21e3d00e6 as it would introduce more dependancies)

Change-Id: I950219b55495604821ccbe59400dd9db7e8270b4
Reviewed-on: https://chromium-review.googlesource.com/356961
Commit-Ready: Harry Pan <harry.pan@intel.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

[modify] https://crrev.com/c7dca2d0386188fdb76e83c45ebaaef3783796a8/arch/x86/kernel/tsc.c

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/51509762819b9b5c64ee3d0e50e9a0acd06bf98b

commit 51509762819b9b5c64ee3d0e50e9a0acd06bf98b
Author: Chen Yu <yu.c.chen@intel.com>
Date: Fri May 06 03:33:39 2016

UPSTREAM: x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO

Currently we read the tsc radio: ratio = (MSR_PLATFORM_INFO >> 8) & 0x1f;

Thus we get bit 8-12 of MSR_PLATFORM_INFO, however according to the SDM
(35.5), the ratio bits are bit 8-15.

Ignoring the upper bits can result in an incorrect tsc ratio, which causes the
TSC calibration and the Local APIC timer frequency to be incorrect.

Fix this problem by masking 0xff instead.

[ tglx: Massaged changelog ]

Fixes: 7da7c1561366 "x86, tsc: Add static (MSR) TSC calibration on Intel Atom SoCs"

BUG=chrome-os-partner:50692, chromium:624029
TEST=dmesg | grep -i tsc # examine TSC calibration flow

Signed-off-by: Chen Yu <yu.c.chen@intel.com>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: stable@vger.kernel.org
Cc: Bin Gao <bin.gao@intel.com>
Cc: Len Brown <lenb@kernel.org>
Link: http://lkml.kernel.org/r/1462505619-5516-1-git-send-email-yu.c.chen@intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

(cherry picked from commit 886123fb3a8656699dff40afa0573df359abeb18)
Signed-off-by: Harry Pan <harry.pan@intel.com>

Change-Id: Ia30d7a583ce606cb9585c0f1e8e620862eb9acee
Reviewed-on: https://chromium-review.googlesource.com/356962
Commit-Ready: Harry Pan <harry.pan@intel.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

[modify] https://crrev.com/51509762819b9b5c64ee3d0e50e9a0acd06bf98b/arch/x86/kernel/tsc_msr.c

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/872e8c343cf32030b1e04e42b916ac73b6207aca

commit 872e8c343cf32030b1e04e42b916ac73b6207aca
Author: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed May 11 15:23:34 2016

UPSTREAM: x86/tsc: Add missing Cherrytrail frequency to the table

Intel Cherrytrail is based on Airmont core so MSR_FSB_FREQ[2:0] = 4
means that the CPU reference clock runs at 80MHz.  Add this missing
frequency to the table.

BUG=chrome-os-partner:50692, chromium:624029
TEST=dmesg | grep -i tsc # examine TSC calibration flow

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Link: http://lkml.kernel.org/r/87y47gty89.fsf@intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

(cherry picked from commit e2724e9d969294879936daf7833d4adda26c8efc)
Signed-off-by: Harry Pan <harry.pan@intel.com>

Change-Id: If6c0fc6e4dc2ea13fafdecb97a3b1043d7bdf2e3
Reviewed-on: https://chromium-review.googlesource.com/356963
Commit-Ready: Harry Pan <harry.pan@intel.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

[modify] https://crrev.com/872e8c343cf32030b1e04e42b916ac73b6207aca/arch/x86/kernel/tsc_msr.c

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/63cbd020425a22bc4fc86e3fe8f49f47b41e91a7

commit 63cbd020425a22bc4fc86e3fe8f49f47b41e91a7
Author: Len Brown <len.brown@intel.com>
Date: Fri Jun 17 05:22:43 2016

UPSTREAM: Revert "x86/tsc: Add missing Cherrytrail frequency to the table"

This reverts commit:

  e2724e9d9692 ("x86/tsc: Add missing Cherrytrail frequency to the table")

... as it is incomplete, and is replaced by a more complete patch
later in this series.

BUG=chrome-os-partner:50692, chromium:624029
TEST=dmesg | grep -i tsc # examine TSC calibration flow

Signed-off-by: Len Brown <len.brown@intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/2199d0e959f7f71a18827268b5d060f8d3831639.1466138954.git.len.brown@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit fc5f3ac24720012909c224a63ca3217f4759967d)
Signed-off-by: Harry Pan <harry.pan@intel.com>

Change-Id: Icc4e673e3bb2770aa63dfaae42d71f73e664aa56
Reviewed-on: https://chromium-review.googlesource.com/356964
Commit-Ready: Harry Pan <harry.pan@intel.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

[modify] https://crrev.com/63cbd020425a22bc4fc86e3fe8f49f47b41e91a7/arch/x86/kernel/tsc_msr.c

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/a130e4032c7b08843d60df7c3d5bb675b6ccb816

commit a130e4032c7b08843d60df7c3d5bb675b6ccb816
Author: Len Brown <len.brown@intel.com>
Date: Fri Jun 17 05:22:44 2016

UPSTREAM: x86/tsc_msr: Identify Intel-specific code

try_msr_calibrate_tsc() is currently Intel-specific,
and should not execute on any other vendor's parts.

BUG=chrome-os-partner:50692, chromium:624029
TEST=dmesg | grep -i tsc # examine TSC calibration flow

Signed-off-by: Len Brown <len.brown@intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1fe23c052826bdcfeb3d45045aa02246078cb5a7.1466138954.git.len.brown@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit ba8268330dc18d309a39175ea4d2c5d86c2cef09)
Signed-off-by: Harry Pan <harry.pan@intel.com>

Change-Id: I9376a6eb116e64ec5cb3b36a183ec7eab59a132d
Reviewed-on: https://chromium-review.googlesource.com/356965
Commit-Ready: Harry Pan <harry.pan@intel.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

[modify] https://crrev.com/a130e4032c7b08843d60df7c3d5bb675b6ccb816/arch/x86/kernel/tsc_msr.c

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/9e515b58c4561a149555a4061b909f5ae291aad8

commit 9e515b58c4561a149555a4061b909f5ae291aad8
Author: Len Brown <len.brown@intel.com>
Date: Fri Jun 17 05:22:45 2016

UPSTREAM: x86/tsc_msr: Remove debugging messages

Debugging messages are not necessary after all of the
possible hardware failures that never occur.
Instead, this code can simply return 0.

This code also doesn't need to print in the success case.
tsc_init() already prints the TSC frequency,
and apic=debug is available if anybody really is
interested in printing the LAPIC frequency.

BUG=chrome-os-partner:50692, chromium:624029
TEST=dmesg | grep -i tsc # examine TSC calibration flow

Signed-off-by: Len Brown <len.brown@intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/cf03279a125b95dfa9b8d3d5b4a66de09cd04050.1466138954.git.len.brown@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit 14bb4e34860af48ef1ea0f52b11611ce4db987fe)
Signed-off-by: Harry Pan <harry.pan@intel.com>

Change-Id: Ib986918623405e8ab2f37c7321a45eeff968459d
Reviewed-on: https://chromium-review.googlesource.com/356966
Commit-Ready: Harry Pan <harry.pan@intel.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

[modify] https://crrev.com/9e515b58c4561a149555a4061b909f5ae291aad8/arch/x86/kernel/tsc_msr.c

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/a75d337b171a2bd12f4b7bc0768e18ee4466e875

commit a75d337b171a2bd12f4b7bc0768e18ee4466e875
Author: Len Brown <len.brown@intel.com>
Date: Fri Jun 17 05:22:46 2016

UPSTREAM: x86/tsc_msr: Update comments, expand definitions

Syntax only, no functional change.

BUG=chrome-os-partner:50692, chromium:624029
TEST=dmesg | grep -i tsc # examine TSC calibration flow

Signed-off-by: Len Brown <len.brown@intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/8653a2dba21fef122fc7b29eafb750e2004d3976.1466138954.git.len.brown@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit 9e0cae9f6227f946fb0076b6a68c88156137f618)
Signed-off-by: Harry Pan <harry.pan@intel.com>

Change-Id: Idcd5f435bd90f0d9b4abf07984ed4328255eedb7
Reviewed-on: https://chromium-review.googlesource.com/356967
Commit-Ready: Harry Pan <harry.pan@intel.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

[modify] https://crrev.com/a75d337b171a2bd12f4b7bc0768e18ee4466e875/arch/x86/kernel/tsc_msr.c

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/02c55f5d2ca8c13c83879a4161563480e50d984b

commit 02c55f5d2ca8c13c83879a4161563480e50d984b
Author: Len Brown <len.brown@intel.com>
Date: Fri Jun 17 05:22:47 2016

UPSTREAM: x86/tsc_msr: Correct Silvermont reference clock values

Atom processors use a 19.2 MHz crystal oscillator.

Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz.

Later preocessor generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz.

Update the Silvermont-based tables accordingly,
matching the Software Developers Manual.

Also, correct a 166 MHz entry that should have been 116 MHz,
and add a missing 80 MHz entry.

BUG=chrome-os-partner:50692, chromium:624029
TEST=dmesg | grep -i tsc # examine TSC calibration flow

Reported-by: Stephane Gasparini <stephane.gasparini@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/5d7561655dfb066ff10801b423405bae4d1cfbe2.1466138954.git.len.brown@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit 05680e7fa8a4e700e031a5e72cd8c18265f0031a)
Signed-off-by: Harry Pan <harry.pan@intel.com>

Change-Id: I33cf76d17712ff48fef8c17f062cea98a336b6ba
Reviewed-on: https://chromium-review.googlesource.com/356968
Commit-Ready: Harry Pan <harry.pan@intel.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

[modify] https://crrev.com/02c55f5d2ca8c13c83879a4161563480e50d984b/arch/x86/kernel/tsc_msr.c

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/0937ac23a18382123c8fa52f93328bf8e2aad635

commit 0937ac23a18382123c8fa52f93328bf8e2aad635
Author: Len Brown <len.brown@intel.com>
Date: Fri Jun 17 05:22:48 2016

UPSTREAM: x86/tsc_msr: Add Airmont reference clock values

per the Intel 64 and IA-32 Architecture Software Developer's Manual...

Add the reference clock for Intel Atom Processors
Based on the Airmont Microarchitecture.

BUG=chrome-os-partner:50692, chromium:624029
TEST=dmesg | grep -i tsc # examine TSC calibration flow

Reported-by: Stephane Gasparini <stephane.gasparini@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/abc6a0f4b18281410da1a3f26e2819d8e03e144f.1466138954.git.len.brown@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit 6fcb41cdaee5056c96de88ee095bddd27a7697de)
Signed-off-by: Harry Pan <harry.pan@intel.com>

Change-Id: I3575ff6d2e7bd6e29a7112e469de480b504e12ec
Reviewed-on: https://chromium-review.googlesource.com/356969
Commit-Ready: Harry Pan <harry.pan@intel.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

[modify] https://crrev.com/0937ac23a18382123c8fa52f93328bf8e2aad635/arch/x86/kernel/tsc_msr.c

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/31205fb0600178d34db5b8351e89f04b70898fc7

commit 31205fb0600178d34db5b8351e89f04b70898fc7
Author: Len Brown <len.brown@intel.com>
Date: Fri Jun 17 05:22:50 2016

UPSTREAM: x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration

Remove the irqoff/irqon around MSR-based TSC enumeration,
as it is not necessary.

Also rename: try_msr_calibrate_tsc() to cpu_khz_from_msr(),
as that better describes what the routine does.

BUG=chrome-os-partner:50692, chromium:624029
TEST=dmesg | grep -i tsc # examine TSC calibration flow

Signed-off-by: Len Brown <len.brown@intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/a6b5c3ecd3b068175d2309599ab28163fc34215e.1466138954.git.len.brown@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit 02c0cd2dcf7fdc47d054b855b148ea8b82dbb7eb)
Signed-off-by: Harry Pan <harry.pan@intel.com>

Change-Id: Iceab73a0a34953b2ad216fc9456e75c364451900
Reviewed-on: https://chromium-review.googlesource.com/356971
Commit-Ready: Harry Pan <harry.pan@intel.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

[modify] https://crrev.com/31205fb0600178d34db5b8351e89f04b70898fc7/arch/x86/include/asm/tsc.h
[modify] https://crrev.com/31205fb0600178d34db5b8351e89f04b70898fc7/arch/x86/kernel/tsc_msr.c
[modify] https://crrev.com/31205fb0600178d34db5b8351e89f04b70898fc7/arch/x86/kernel/tsc.c

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/b90d5e845bc2e812ab1d88cafe0240ef547dbcd5

commit b90d5e845bc2e812ab1d88cafe0240ef547dbcd5
Author: Len Brown <len.brown@intel.com>
Date: Fri Jun 17 05:22:51 2016

UPSTREAM: x86/tsc: Enumerate SKL cpu_khz and tsc_khz via CPUID

Skylake CPU base-frequency and TSC frequency may differ
by up to 2%.

Enumerate CPU and TSC frequencies separately, allowing
cpu_khz and tsc_khz to differ.

The existing CPU frequency calibration mechanism is unchanged.
However, CPUID extensions are preferred, when available.

CPUID.0x16 is preferred over MSR and timer calibration
for CPU frequency discovery.

CPUID.0x15 takes precedence over CPU-frequency
for TSC frequency discovery.

BUG=chrome-os-partner:50692, chromium:624029
TEST=dmesg | grep -i tsc # examine TSC calibration flow

Signed-off-by: Len Brown <len.brown@intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/b27ec289fd005833b27d694d9c2dbb716c5cdff7.1466138954.git.len.brown@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit aa297292d708e89773b3b2cdcaf33f01bfa095d8)
Signed-off-by: Harry Pan <harry.pan@intel.com>

Conflicts:
	arch/x86/kernel/tsc.c
(Conflict w/ 6dcbe15a8df7: CHROMIUM: Write the initial TSC at early
kernel init)

Change-Id: Ide0b7b13e9c3d16a8bd0c0ad251929534fe6d439
Reviewed-on: https://chromium-review.googlesource.com/356972
Commit-Ready: Harry Pan <harry.pan@intel.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

[modify] https://crrev.com/b90d5e845bc2e812ab1d88cafe0240ef547dbcd5/arch/x86/kernel/x86_init.c
[modify] https://crrev.com/b90d5e845bc2e812ab1d88cafe0240ef547dbcd5/arch/x86/include/asm/tsc.h
[modify] https://crrev.com/b90d5e845bc2e812ab1d88cafe0240ef547dbcd5/arch/x86/kernel/tsc.c
[modify] https://crrev.com/b90d5e845bc2e812ab1d88cafe0240ef547dbcd5/arch/x86/include/asm/x86_init.h

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/c9f290ab9c2fa5a1b1f62b3f86282d0a9216fd4e

commit c9f290ab9c2fa5a1b1f62b3f86282d0a9216fd4e
Author: Len Brown <len.brown@intel.com>
Date: Fri Jun 17 05:22:52 2016

UPSTREAM: x86/tsc: Enumerate BXT tsc_khz via CPUID

Hard code the BXT crystal clock (aka ART - Always Running Timer)
to 19.200 MHz, and use CPUID leaf 0x15 to determine the BXT TSC frequency.

Use tsc_khz to sanity check BXT cpu_khz,
which can be erroneous in some configurations.

(I simplified the original patch from Bin Gao.)

BUG=chrome-os-partner:50692, chromium:624029
TEST=dmesg | grep -i tsc # examine TSC calibration flow

Original-From: Bin Gao <bin.gao@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/bf4e7c175acd6d09719c47c319b10ff1f0627ff8.1466138954.git.len.brown@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit ff4c86635ee12461fd3bd911d7d5253394da8f9d)
Signed-off-by: Harry Pan <harry.pan@intel.com>

Change-Id: Ie2f03036dc0b2725c51263b0b994ce93209bfd96
Reviewed-on: https://chromium-review.googlesource.com/356973
Commit-Ready: Harry Pan <harry.pan@intel.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

[modify] https://crrev.com/c9f290ab9c2fa5a1b1f62b3f86282d0a9216fd4e/arch/x86/kernel/tsc.c

The following revision refers to this bug:
  https://chromium.googlesource.com/chromiumos/third_party/kernel/+/41fef4eb8c23352f6175c9a16c8d7e0b7e66520e

commit 41fef4eb8c23352f6175c9a16c8d7e0b7e66520e
Author: Wei Jiangang <weijg.fnst@cn.fujitsu.com>
Date: Fri Jul 15 08:12:10 2016

UPSTREAM: x86/tsc: Remove the unused check_tsc_disabled()

check_tsc_disabled() was introduced by commit:

  c73deb6aecda ("perf/x86: Add ability to calculate TSC from perf sample timestamps")

The only caller was arch_perf_update_userpage(), which had been refactored
by commit:

  d8b11a0cbd1c ("perf/x86: Clean up cap_user_time* setting")

... so no need keep and export it any more.

BUG=chrome-os-partner:50692, chromium:624029
TEST=dmesg | grep -i tsc # examine TSC calibration flow

Signed-off-by: Wei Jiangang <weijg.fnst@cn.fujitsu.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: a.p.zijlstra@chello.nl
Cc: adrian.hunter@intel.com
Cc: bp@suse.de
Link: http://lkml.kernel.org/r/1468570330-25810-1-git-send-email-weijg.fnst@cn.fujitsu.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit c48ec42d6eae08f55685ab660f0743ed33b9f22a)
Signed-off-by: Harry Pan <harry.pan@intel.com>

Change-Id: I6931bfbc700c7e25a9fe55bae2d33f5d264615b2
Reviewed-on: https://chromium-review.googlesource.com/363311
Commit-Ready: Harry Pan <harry.pan@intel.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

[modify] https://crrev.com/41fef4eb8c23352f6175c9a16c8d7e0b7e66520e/arch/x86/include/asm/tsc.h
[modify] https://crrev.com/41fef4eb8c23352f6175c9a16c8d7e0b7e66520e/arch/x86/kernel/tsc.c

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