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Issue metadata

Status: WontFix
Owner:
Closed: Jun 2018
Cc:
Components:
EstimatedDays: ----
NextAction: ----
OS: ----
Pri: 3
Type: Bug



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Serial port on Skylake is not working

Project Member Reported by dbehr@chromium.org, May 11 2016

Issue description

Serial port on servo does not work on Chell or Lars.
There is a PCI device 8086:9D66 which has serial port but the serial driver does not detect it.

i ended up doing this 

--diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
index beb9d71..e1c21ce 100644
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -1355,6 +1355,8 @@ ce4100_serial_setup(struct serial_private *priv,
 #define PCI_DEVICE_ID_INTEL_BSW_UART1  0x228a
 #define PCI_DEVICE_ID_INTEL_BSW_UART2  0x228c
 
+#define PCI_DEVICE_ID_INTEL_SKL_UART2  0x9d66
+
 #define BYT_PRV_CLK                    0x800
 #define BYT_PRV_CLK_EN                 (1 << 0)
 #define BYT_PRV_CLK_M_VAL_SHIFT                1
@@ -2783,6 +2785,7 @@ enum pci_board_num_t {
        pbn_ADDIDATA_PCIe_8_3906250,
        pbn_ce4100_1_115200,
        pbn_byt,
+       pbn_skl,
        pbn_qrk,
        pbn_omegapci,
        pbn_NETMOS9900_2s_115200,
@@ -3534,6 +3537,14 @@ static struct pciserial_board pci_boards[] = {
                .uart_offset    = 0x80,
                .reg_shift      = 2,
        },
+
+       [pbn_skl] = {
+               .flags          = FL_BASE0,
+               .num_ports      = 1,
+               .base_baud      = 115200,
+               .reg_shift      = 2,
+       },
+
        [pbn_qrk] = {
                .flags          = FL_BASE0,
                .num_ports      = 1,
@@ -5248,6 +5259,11 @@ static struct pci_device_id serial_pci_tbl[] = {
                PCI_ANY_ID,  PCI_ANY_ID,
                PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
                pbn_byt },
+       /* Intel Skylake */
+       {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_UART2,
+               PCI_ANY_ID,  PCI_ANY_ID,
+               PCI_BASE_CLASS_SIGNAL_PROCESSING << 16, 0xff0000,
+               pbn_skl },
 
        /*
         * Intel Quark x1000

Which is a bit hacky and probably needs few extra register writes to take it out of reset and switch to mmio32 mode in case coreboot does not do it.

Or maybe it should be enabled via Intel LPSS MFD driver?
 
I don't think I ever tried using kernel serial console without having coreboot set it up first and passing 'console=uart8250,mmio32,0xfe034000,115200n8' to the kernel.

Comment 2 by snanda@chromium.org, May 11 2016

Cc: snanda@chromium.org
Owner: tbroch@chromium.org
Components: OS>Kernel
Status: WontFix (was: Untriaged)
closing since device has long since shipped 

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